Georgios I. Stamoulis

A Monte Carlo approach for maximum power estimation based on extreme value theory

A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed. The approach is based on the largely unexploited area of statistics known as extreme value theory. Within this framework, it attempts to appropriately model the extreme behavior of the probability distribution of the peak instantaneous power drawn from the power supply bus, in order to yield a close estimate of its maximum possible value. The approach features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels for the final estimate, simplicity in the algorithmic implementation, noniterative single-loop execution, highly accurate simulation-based operation, and easy integration within the design flow of CMOS VLSI circuits. Experimental results establish the above claims and demonstrate the overall efficiency of the proposed approach to address the problem of maximum power estimation.

Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects

Probabilistic simulation has been shown to be a very cost-effective approach to the computation of voltage and current waveform statistics in CMOS digital circuits, compared to exhaustive simulation. This approach is particularly attractive when long-term reliability issues such as electromigration, hot-carrier effects, and average power, are to be estimated over all possible input signals. In this paper we present new algorithms for performing probabilistic simulation that provide significant improvements over existing ones, both in accuracy and speed. The improvements are carried out at the subcircuit level, where the statistics of the current and voltage waveforms and the delays are computed more accurately, and at the global level, where signal correlations are considered. The new algorithms have been implemented in a computer program and tested on a number of large benchmark circuits.

A low-power/low-noise readout circuit for integrated capacitive sensors

A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-muW average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8% linearity error and 0.01 fF/degC temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing

A probabilistic timing approach to hot-carrier effect estimation

In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks. >

iProbe-d: a hot-carrier and oxide reliability simulator

In this paper we describe a hot-carrier and oxide reliability simulator, iProbe-d. In this program, a probabilistic timing approach is employed to find the most susceptible devices to hot-carrier degradation and/or oxide breakdown in a CMOS VLSI digital circuit design under expected operating conditions. After the damage in each device is determined, a combination of damaged-transistor model, RC delay and critical path analysis is used to estimate the impact of hot-carrier effects (HCE) on circuit performance; namely, the increase of circuit delay. The results can then be used to improve the reliability of the circuit prior to fabrication.<<ETX>>

A high performance and low power hardware architecture for the transform & quantization stages in H.264

In this work, we present a hardware architecture prototype for the various types of transforms and the accompanying quantization, supported in H.264 baseline profile video encoding standard. The proposed architecture achieves high performance and can satisfy Quad Full High Definition (QFHD) (3840·2160@150Hz) coding. The transforms are implemented using only add and shift operations, which reduces the computation overhead. A modification in the quantization equations representation is suggested to remove the absolute value and resign operation stages overhead. Additionally, a post-scale Hadamard transform computation is presented. The architecture can achieve a reduction of about 20% in power consumption, compared to existing implementations.

A Monte-Carlo approach for the accurate and efficient estimation of average transition probabilities in sequential logic circuits

This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

Precise identification of the worst-case voltage drop conditions in power grid verification

Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology for power grid verification which is based on accurately constructing the space of current variations of the supplied modules and locating its precise points that yield the worst-case voltage drop conditions. The construction of the current space is performed via plain simulation and statistical extrapolation using results from extreme value theory. The method overcomes limitations of past methods which either relied on loosely bounding the worst-case voltage drop, or abstracted the current space in a vague and incomplete set of bound-type constraints. Experimental results verify the potential of the proposed method to identify worst-case conditions and demonstrate the pessimism inherent in previous bound-type approaches

A Novel Low-Power Motion Estimation Design for H.264

The H.264 video coding standard can achieve considerably higher coding efficiency than previous video coding standards. The keys to this high coding efficiency are the two prediction modes (Intra & Inter) provided by H.264 which adopt many new features such as variable block size searching, motion vector prediction etc. However, these result in a considerably higher encoder complexity that adversely affects speed and power, which are both significant for the mobile multimedia applications targeted by the standard. Therefore, it is of high importance to design architectures that minimize the speed and power overhead of the prediction modes. In this paper we present a new algorithm, and the architecture that implements it, that can replace the standard sum of absolute differences (SAD) approach in the two main prediction modes, supports the variable block size motion estimation (VBSME) as it is defined in the standard and provide a power efficient hardware implementation without perceivable degradation in coding efficiency or video quality.

A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions

Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important design parameter. Unfortunately high precision analysis is expensive in computer execution time, and there is always a trade-off between accuracy and speed. This work proposes a new circuit simulation approach by storing a set of pre-characterized transition configurations for each standard library cell in a lookup table. The lookup table contains information about the voltage and the current transient waveform produced by SPICE simulation. The method achieves good accuracy levels for yielding the total or partial current waveform of a circuit in significantly less time compared to SPICE or other commercial tools.