Michael E. Wazlowski

Pinnacle: IBM MXT in a memory controller chip

Pinnacle leverages state-of-the-art technologies to establish a low-cost, high-performance single-chip memory controller. The chip uses IBMs memory expansion technology system architecture, which more than doubles the installed main memorys effective size without adding significant cost or degrading performance.

Blue Gene/L compute chip: memory and Ethernet subsystem

The Blue Gene®/L compute chip is a dual-processor system-on-a-chip capable of delivering an arithmetic peak performance of 5.6 gigaflops. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-chip cache hierarchy. The implemented hierarchy offers high bandwidth and integrated prefetching on cache hierarchy levels 2 and 3 (L2 and L3) to reduce memory access time. A Gigabit Ethernet interface driven by direct memory access (DMA) is integrated in the cache hierarchy, requiring only an external physical link layer chip to connect to the media. The integrated L3 cache stores a total of 4 MB of data, using multibank embedded dynamic random access memory (DRAM). The 1,024-bit-wide data port of the embedded DRAM provides 22.4 GB/s bandwidth to serve the speculative prefetching demands of the two processor cores and the Gigabit Ethernet DMA engine. To reduce hardware overhead due to cache coherence intervention requests, memory coherence is maintained by software. This is particularly efficient for regular highly parallel applications with partitionable working sets. The system further integrates an on-chip double-data-rate (DDR) DRAM controller for direct attachment of main memory modules to optimize overall memory performance and cost. For booting the system and low-latency interprocessor communication and synchronization, a 16-KB static random access memory (SRAM) and hardware locks have been added to the design.

Server-class DDR3 SDRAM memory buffer chip

IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability for the double-data-rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) subsystems employed across a wide range of server platforms. The new IBM AMB employs a cyclic redundancy code-protected packet-protocol-based 6.4-Gb/s host channel, as well as dual 9-byte/10-byte wide 800 to 1,333-Mb/s SDRAM interfaces with dynamic calibration for optimal signal integrity under varied device and system environmental conditions. Applications support industry-standard dual inline memory module (DIMM) and low-latency high-capacity proprietary DIMM packages in conventional multichannel and redundant array of independent memory system architectures. A fully configured daisy-chain topology contains up to 256 GB of memory per host channel. This paper describes the IBM AMB chip architecture, design, and key engineering aspects.

Verification strategy for the Blue Gene/L chip

The Blue Gene®/L compute chip contains two PowerPC® 440 processor cores, private L2 prefetch caches, a shared L3 cache and double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory controller, a collective network interface, a torus network interface, a physical network interface, an interrupt controller, and a bridge interface to slower devices. System-on-a-chip verification problems require a multilevel verification strategy in which the strengths of each layer offset the weaknesses of another layer. The verification strategy we adopted relies on the combined strengths of random simulation, directed simulation, and code-driven simulation at the unit and system levels. The strengths and weaknesses of the various techniques and our reasons for choosing them are discussed. The verification platform is based on event simulation and cycle simulation running on a farm of Intel-processor-based machines, several PowerPC-processor-based machines, and the internally developed hardware accelerator Awan. The cost/performance tradeoffs of the different platforms are analyzed. The success of the first Blue Gene/L nodes, which worked within days of receiving them and had only a small number of undetected bugs (none fatal), reflects both careful design and a comprehensive verification strategy.

On management of free space in compressed memory systems

This paper considers issues relevant to Operating System control of systems with compressed main memory. The notion of “allocated but unused storage” is introduced. This represents storage which has been recently allocated by the Operating System, but which does not yet occupy physical memory because the lines have not yet been cast out of the cache. We propose that control policies incorporate estimates of allocated but unused storage , as such storage represents a major way in which compressibility can dramatically change. The paper addresses the estimation of allocated but unused storage and analyzes its accuracy on system traces.

Reliability-availability-serviceability characteristics of a compressed-memory system

New compression innovations and high-density silicon technology enable us to introduce main-memory compression. This technology is able to achieve, in most cases, 2:1 or better compression without impacting performance. It provides an enormous cost/performance advantage, given the cost content of memory in modern enterprise servers. The complex and highly parallel data manipulations central to this compression implementation would, if unprotected by extensive error detection and error correction techniques, offer several potential data integrity exposures. This paper describes the memory subsystem of an enterprise class server with a compressed mainstore and the methods which have been employed to guarantee the integrity of the compressed data. These methods consist of a novel ECC algorithm which includes address information in the code words, the use of CRC codes for compressed data blocks, and various consistency checks on the memory management structures used in the management of a compressed mainstore.