Robert B. Tremaine

Server-class DDR3 SDRAM memory buffer chip

IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability for the double-data-rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) subsystems employed across a wide range of server platforms. The new IBM AMB employs a cyclic redundancy code-protected packet-protocol-based 6.4-Gb/s host channel, as well as dual 9-byte/10-byte wide 800 to 1,333-Mb/s SDRAM interfaces with dynamic calibration for optimal signal integrity under varied device and system environmental conditions. Applications support industry-standard dual inline memory module (DIMM) and low-latency high-capacity proprietary DIMM packages in conventional multichannel and redundant array of independent memory system architectures. A fully configured daisy-chain topology contains up to 256 GB of memory per host channel. This paper describes the IBM AMB chip architecture, design, and key engineering aspects.

Verification strategy for the Blue Gene/L chip

The Blue Gene®/L compute chip contains two PowerPC® 440 processor cores, private L2 prefetch caches, a shared L3 cache and double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory controller, a collective network interface, a torus network interface, a physical network interface, an interrupt controller, and a bridge interface to slower devices. System-on-a-chip verification problems require a multilevel verification strategy in which the strengths of each layer offset the weaknesses of another layer. The verification strategy we adopted relies on the combined strengths of random simulation, directed simulation, and code-driven simulation at the unit and system levels. The strengths and weaknesses of the various techniques and our reasons for choosing them are discussed. The verification platform is based on event simulation and cycle simulation running on a farm of Intel-processor-based machines, several PowerPC-processor-based machines, and the internally developed hardware accelerator Awan. The cost/performance tradeoffs of the different platforms are analyzed. The success of the first Blue Gene/L nodes, which worked within days of receiving them and had only a small number of undetected bugs (none fatal), reflects both careful design and a comprehensive verification strategy.

IBM system z10 open systems adapter ethernet data router

The IBM Open Systems Adapter (OSA) is a family of integrated hardware features that enables direct connection between IBM System z10™ hosts and clients on local area networks (LANs). The OSA provides a virtual interface to the LAN that may be shared by hundreds of host operating systems. The newest OSA generation employs a hardware-based Ethernet virtualization offload engine to significantly increase throughput and reduce latency in line with the latest 1-Gb and 10-Gb Ethernet adapters. The router is embodied in the OSA Ethernet data router ASIC (application-specific integrated circuit) chipset and is packaged in several configurations. This paper describes the function of the OSA Ethernet data router, its hardware architecture, and the implementation of the design.