Michael F. Lofaro

Ultra Low Contact Resistivities for CMOS Beyond 10-nm Node

Contact resistances are directly measured for contacts with sizes from 25 to 330 nm using e-beam based nano-TLM devices. Record low contact resistivities ~1.5 × 10^-9 Ω· cm² are extracted from Ni(Pt) silicide contacts on in situ boron-doped Si_0.7Ge_0.3 with a chemical boron-doping density of 2 × 10²¹/cm³. This is very promising for pMOS applications beyond the 10-nm node. A clear dependence of contact resistance on the silicide thickness has also been found.

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L_G=21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W_FIN) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT~7Å, and excellent μ_eff=220cm²/Vs at N_inv=10¹³ for fins with W_FIN~4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

Resistivity of copper interconnects beyond the 7 nm node

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs. We also present some structural details of the gate stack, for the first time. Short channel characteristics of HGC SiGe FinFETs have also been studied for various fin widths. Compared to our earlier RMG work, improved I/I free process with ultra-thin spacers has led to considerable R<inf>on</inf> and R<inf>ext</inf> reduction. As a result, we have demonstrated very high SiGe performance with I<inf>on</inf>=0.45mA/μm at I<inf>off</inf>=100nA/μm at V<inf>dd</inf>=0.5V for L<inf>G</inf>=25nm, matching our record for gate-first SiGe FinFETs and outperforming the gate-first results at such LG.

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.

200 mm wafer-scale integration of sub-20 nm sacrificial nanofluidic channels for manipulating and imaging single DNA molecules

We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged by fluorescence microscopy. Our method offers a manufacturable wafer-scale approach for CMOS-compatible bio-chip platform.

Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm 2

The resistivity of damascene Cu is measured at cross-sectional area as low as 95 nm2. The impact of aspect ratio and line edge roughness on resistivity is investigated. Kelvin resistance test structures are demonstrated with 28 nm pitch wires patterned by directed self-assembly of lamellar block copolymers. The effective resistivity of TaN/Ta/Cu wires is compared with alternative metals.