Mahadevaiyer Krishnan

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

3. FEOL Applications: Device Level 180 3.1. Shallow Trench Isolation (STI) CMP 180 3.2. Replacement Metal Gate CMP 184 3.3. Poly-Si CMP for FinFET Devices 186 4. MOL Applications: Contact Level 187 4.1. Tungsten CMP 187 5. BEOL Applications: Multilevel Interconnects 188 5.1. Copper Interconnect Technology 188 5.2. CMP Challenges in Cu Interconnects 189 5.2.1. Low-k and Ultralow-k Material Challenges 189 5.2.2. Integration Challenges 190 5.2.3. CMP Process Challenges 191 5.3. Copper Planarizarion Process 191 5.4. Ta/TaN Liner CMP Process 193 6. CMP Process-Induced Defects 194 6.1. Defects in FEOL CMP 194 6.2. Defects in MOL Tungsten CMP 195 6.3. Defects in Cu BEOL CMP 195 6.3.1. Corrosion of Copper 196 6.3.2. Scratches 196 6.3.3. Dishing, Erosion, and Trenching 196 6.3.4. Mechanical Damage 197 6.3.5. Other Defects 197 7. Models of CMP Processes 198 7.1. Models Based on Contact Mechanics 198 7.2. CMP Process Models 199 8. Alternative CMP Processes 200 9. Concluding Remarks 201 10. Acknowledgments 201 11. References 201

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

Electroless plating of copper at a low pH level

A new process for electroless copper plating at a pH level of ≤9 is described. The process uses amine borane reducing agents and ligands based on neutral tetradentate nitrogen donors. The use of a variety of buffer systems is demonstrated. Electroless bath performance over a wide range of conditions is presented. The quality of the plated copper is comparable to that obtained by currently used electroless plating processes, and has a resistivity of about 1.8-2 µΩ-cm, depending on bath composition and process parameters. Use of the process is illustrated for forming conductors and filling via holes having submicron minimum dimensions.

Multilayer epitaxial graphene formed by pyrolysis of polycrystalline silicon-carbide grown on c-plane sapphire substrates

We use ultrahigh vacuum chemical vapor deposition to grow polycrystalline silicon carbide (SiC) on c-plane sapphire wafers, which are then annealed between 1250 and 1450 °C in vacuum to create epitaxial multilayer graphene (MLG). Despite the surface roughness and small domain size of the polycrystalline SiC, a conformal MLG film is formed. By planarizing the SiC prior to graphene growth, a reduction in the Raman defect band is observed in the final MLG. The graphene formed on polished SiC films also demonstrates significantly more ordered layer-by-layer growth and increased carrier mobility for the same carrier density as the nonpolished samples.

Measuring layer-specific depth-of-focus requirements

As the Rayleigh equations already tell us, improvements in imaging resolution often come at the price of a depth-offocus loss. Often we balance the resolution versus DoF dilemma without regard of the imaging layers location in the overall film stack. E.g. often several via or metal layers are processed with the same optical settings despite facing different amount of depth-of-focus requirements. In actuality, however, substrate induced focus variation can vary greatly from layers at the bottom of a film stack to the layers higher up in the film stack. In the age of super-low k1 lithography this variance needs to be taken into account on a layer specific basis when evaluating the resolution versus DoF tradeoff. We have studied substrate induced focus variation for a 45nm technology test-site as function of film stack sequence and spatial frequency, combining various measurement techniques into an overall topography spectrum. These techniques include data extraction from the exposure tools optical leveling sensor, a mechanical air gauge to calibrate the former and interferometric profiling tools. As a result, we can quantify our DoF requirement for a given layer and product and use this information to optimize our process design on a layer-by-layer basis. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities