Michael F. McAllister

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Frequency dependencies of power noise

In this paper, frequency dependencies of delta-I noise caused by variations of the on-chip switching activity have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching frequency and the noise source waveform have been varied in case of a single delta-I step. For repeated delta-I steps the power noise dependencies on the repetition frequency, the duty cycle and the damping of the resonant loop have been analyzed. Simulations using switching current sources for on-chip switching have been confirmed by simulations with switching resistors plus de voltage source. Mid-frequency noise simulations using SPEED2000 and noise voltage measurements yield the same results within 6% for the first and second voltage droops and overshoots, if the real resistance of power/ground vias and module pins are included in the simulation.

Measurement of dielectric anisotropy of BPDA-PDA polyimide in multilayer thin-film packages

The measured dielectric anisotropy of BPDA-PDA polyimide, obtained from a specially designed test vehicle, is presented. The multilayer thin-film structure is representative of its actual use in multichip carrier (MCM-D) applications both from the cross sectional dimensions and fabrication sequence point of view. Modeling is performed using finite-element and electromagnetic techniques and the effect of anisotropy on signal propagation and crosstalk are verified through time-domain measurements. >

Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%.