Wiren D. Becker

When are transmission-line effects important for on-chip interconnections?

Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Modeling, measurement, and simulation of simultaneous switching noise

The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power distribution is very challenging since it requires accurate models of active devices, passive components, transmission lines, and a very large power distribution network. This paper presents the development of a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metal-oxide-semiconductor (CMOS) chip on a multilayered ceramic substrate. Measurements are performed on a CMOS chip with simultaneously switching off-chip drivers (OCDs). The modeling approach is validated by the excellent agreement between the measurement waveforms and simulation results.

When are transmission-line effects important for on-chip interconnections

Short, medium and long on-chip interconnections having line widths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Efficient modeling of power planes in computer packages using the finite difference time domain method

Recent advancements in electronic packaging, that have led to the development of high speed devices with increasingly high interconnect densities, have precipitated the need to incorporate high frequency effects in the modeling of these structures. The Finite Difference Time Domain (FDTD) method is not only well-suited for handling the complex geometries involved, but is also useful for generating the desired frequency response with a single simulation. In this paper, we describe several techniques for improving the computational efficiency of the conventional FDTD algorithm as applied to the problem of modeling complex power plane geometries. We also show how the time domain response can be processed to extract equivalent circuits that are valid in the high frequency regimes up to several GHz, and are suitable for use in circuit simulators. >

The importance of inductance and inductive coupling for on-chip wiring

The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.

MCM technology and design for the S/390 G5 system

The multichip module (MCM) that contains the central electronic complex (CEC) of the S/390 G5 system is described in this paper. The glass-ceramic module, topped with six layers of polyimide full-field thin-film wiring for chipto-chip interconnection, represents IBM’s most advanced packaging technology. This MCM provides a large wiring capacity, with 595 meters of routed interconnection; it supports the highest synchronous interconnection performance in the industry at 300 MHz; and it allows for cooling flexibility at the system level—either a heat sink for air-cooled systems or a cooling “hat” for systems using refrigeration cooling. The physical and electrical characteristics of this packaging technology, necessary to support the aggressive system performance goals (1040 MIPS) of the IBM G5 Enterprise Servers, are presented here. In addition, the approach used to produce a robust electrical and physical design is described.

Power distribution modelling of high performance first level computer packages

A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-layered computer package is shown. Semiconductor chips and decoupling capacitors are placed on the top surface of the package and the module is connected to a board or card for communication with other components of the computer. A schematic of the final inductance model of a multi-layered ceramic single chip module used in computer products is shown.<<ETX>>

First- and second-level packaging of the z990 processor cage

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

Mid-frequency simultaneous switching noise in computer systems

CMOS microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity from clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50 to 200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm MCM on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.