Michael Fulde

LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology

In this brief, a conventional LC voltage-controlled oscillator (LC-VCO) for Global System for Mobile Communications 900 applications is implemented in a 32-nm CMOS technology. The transition to 32-nm technology represents a big step from the technological point of view, mainly due to the introduction of high-κ dielectrics. In spite of the considered ultrascaled technology, the measured performance is aligned with recently published conventional LC-VCOs in the gigahertz range. The robustness of the VCO versus temperature and supply variation is experimentally characterized and analyzed in detail by means of circuit simulations.

13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS

The evolving trend for increasing data rates in cellular communication systems with limited and fragmented frequency spectrum requires enhanced spectral efficiency of todays and future communication standards. The resulting need for high-order modulation schemes with large peak-to-average power ratio results in stringent requirements on in-channel linearity and SNR. At the same time FDD operation in SAW filter-less designs enforces very demanding limits for out-of-band and spurious emissions. Digital polar TX concepts have demonstrated low power consumption combined with low out-of-band noise in moderate bandwidth applications like WCDMA [1]. However, the implementation of 4G wideband polar systems with 20MHz RF bandwidth and above is very challenging due to the nonlinear conversion from cartesian to polar coordinates extending the effective signal bandwidth even further. A digital quadrature TX concept with up to 80MHz bandwidth, low EVM and moderate power efficiency has been shown in [2]. More than 30% power-added efficiency has been demonstrated in a 20MHz polar TX based on a switched-capacitor digital PA [3]. However, [2,3] suffer from low resolution and limited out-of-band noise performance.

A Nonlinear Switched State-Space Model for Capacitive RF DACs

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements.