Michael G. Gallup

Testability features of the 68040

The design and implementation of on-chip test functions on the 68040 microprocessor are described. The discussion includes an introduction to the 68040, along with the testability goals and objectives that were set at the beginning of the design. Further discussions detail the different design-for-testability techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the 68040.<<ETX>>

The 68040 processor. I. Design and implementation

The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.<<ETX>>

IMPLEMENTING 1149.1 ON CMOS MICROPROCESSORS

Selected implementation issues of IEEE 1149.1 Std. Test Access Port and Boundary-Scan Architecture are described for three Motorola VLSI CMOS microprocessors. F’roblems and solutions that arose during implementation of standard features and additional public instructions are discussed.

The 68040 processor. 2. Memory design and chip

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed.<<ETX>>

Test architecture of the Motorola 68040

The 68040 is a third generation 32-bit microprocessor that implements the 68000 family instruction set. The philosophy for the design for test (DFT) effort on the 68040 is to address each class of logic in a different manner. In it there is the typical breakdown of data paths, ROM/PLA structures, embedded RAMs, random logic (sequential and nonsequential), and finite state machines. In each of these areas a different DFT style is used. The test logic architecture that is implemented to allow more thorough test coverage is discussed. The different test modes of the chip are detailed. In order to assist the customer in board-level testing, the 68040 implements the IEEE 1149.1 (JTAG) interface. Also discussed are the Motorola additions to the JTAG interface.<<ETX>>

Case study of 1149.01 microprocessor implementations

Abstract This paper describes selected implementation issues of IEEE 1149.1 Std. Test Access Port and Boundary-Scan Architecture for three Motorola VLSI CMOS microprocessors. Problems and solutions that arose during implementation of standard features and additional public instructions are discussed.