Ralph McGarity

Testability features of the 68040

The design and implementation of on-chip test functions on the 68040 microprocessor are described. The discussion includes an introduction to the 68040, along with the testability goals and objectives that were set at the beginning of the design. Further discussions detail the different design-for-testability techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the 68040.<<ETX>>

The 68040 processor. I. Design and implementation

The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.<<ETX>>

The 68040 on-chip memory subsystem

The Motorola 68040 is a third-generation, high-performance, full 32-b microprocessor. The caches, memory-management units (MMUs), and autonomous controllers for the caches and external bus that comprise the memory subsystem are described. The 68040s memory subsystem supports the performance of the integer and floating-point units by using autonomous internal cache/MMU controllers in a Harvard architecture. Physical caches of 4 kB each for instruction and data are provided. The data cache operates in copyback or write-through mode on a per-page basis. Combined with each cache is a separate address translation cache of 64 entries and two transparent translation registers that operate in parallel with the cache to provide complete memory management in a virtual, demand-page environment. The memory subsystem is designed to provide the majority of the required memory bandwidth for the internal caches. The 68040 has two MMUs: one for instruction logical-to-physical address translation and one for data address translation. High performance is possible owing in part to the high level of concurrency available in the memory subsystem.<<ETX>>

The Design And Implementation of the MC68851 Paged Memory Management Unit

Pipelining, microsequencer start-up in parallel with bus arbitration, and a fully associative translation cache enhanced the performance of this 32-bit memory management device.

The 68040 integer and floating-point units

The integer, floating-point, and on-chip memory subsystems of the Motorola 68040 microprocessor operate in parallel to achieve four times the performance of a 68020 microprocessor and ten times the performance of a 68882 floating-point coprocessor. The integer and floating-point units are described in terms of their performance, internal architecture, and methods used to obtain this performance. The 68040 integer unit (IU) is optimized to execute the most common instructions in a single cycle while maintaining user code compatibly with the 68000 family. To increase performance, the 68040 reduces both the number of arithmetic logic unit (ALU) cycles per instruction (CPI) and the ALU cycle time. The 68040 has a six-stage pipe consisting of an instruction prefetch stage, a program counter calculation and decode stage, an effective address calculation stage for operands, a data execute stage, and a write-back stage. The 68040 floating-point unit (FPU) conforms to the IEEE 754 floating-point standard via a software envelope.<<ETX>>

The 68040 processor. 2. Memory design and chip

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed.<<ETX>>

Experiments with the SLIM Circuit Compactor

Experiments performed with the SLIM symbolic circuit compactor are described. The experiments were designed to compare SLIM created modules to manually created modules, to attempt to find performance predictors for SLIM, and to determine how well SLIM would compact modules created by a synthesis-by-refinement program. The results indicate that SLIM compacts modules which will be created by this program as area efficiently as it compacts modules created by other methods. Also, a performance predictor which estimates the area required by SLIM generated modules was developed. Finally, it was found that SLIMs designs are larger than manual designs by 60% to 90%.