Michael Hack

A new analytic model for amorphous silicon thin-film transistors

We present a new theory describing current‐voltage characteristics of amorphous silicon thin‐film transistors. We calculate the output conductance in saturation by considering channel shortening effects caused by the space‐charge‐limited current in the pinch‐off region. In this model the drain current is expressed through the free‐carrier concentration at the source side of the channel. This allows us to obtain an accurate description of the different operating regimes of a thin‐film transistor using one equation that accounts for the dependence of the free‐carrier concentration in the channel for different regimes. Our model is in good agreement both with experimental data and the results of our two‐dimensional computer simulation. This approach allows one to account for different distributions of localized states in the energy gap. The model has also been developed to be incorporated into a circuit simulator and used for computer‐aided design of amorphous silicon integrated circuits.

Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.

Physical models for degradation effects in polysilicon thin-film transistors

Experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. A model is proposed to explain these effects whereby device performance degrades due to changes in the effective density of defect states in the material. Unlike single-crystal devices which degrade from hot-carrier effects, poly-Si TFTs are believed to degrade primarily due to the presence of high carrier densities in the channel. Good agreement between computer simulations of the device characteristics and experimental data ia demonstrated. It is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady-state conditions. >

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

Avalanche-induced effects in polysilicon thin-film transistors

A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices.<<ETX>>

Effective density‐of‐states distributions for accurate modeling of polycrystalline‐silicon thin‐film transistors

The effective density‐of‐states (DOS) distributions in unhydrogenated and hydrogenated polycrystalline silicon (poly‐Si) thin films have been determined from field‐effect conductance measurements of n‐ and p‐channel thin‐film transistors (TFTs) fabricated in these films. These results are compared with those obtained through device simulation as well as with trap‐state densities obtained by Levinson’s method. Variations in TFT fabrication process conditions and device architecture are shown to significantly impact the DOS distribution and to correspondingly affect device performance. Hydrogenated low‐temperature‐processed (600u2009°C) films have relatively high midgap‐state and valence‐band tail‐state densities and Fermi levels located above midgap, in contrast to high‐temperature‐processed (950u2009°C) films that have low midgap‐state densities and Fermi levels located below midgap. The field‐effect conductance analysis method provides realistic gap‐state density information and can thereby facilitate the accura...

An analytic model for calculating trapped charge in amorphous silicon

We present a simple analytic model for calculating the trapped‐charge density as a function of free‐carrier concentration for realistic density‐of‐states distributions in hydrogenated amorphous silicon. This is necessary to understand the behavior of amorphous silicon devices as their characteristics are largely determined by the high concentration of charge trapped by the localized stages in the band gap. Such a model is useful as an aid in exploring the nature of the charge‐trapping process and for the efficient numerical simulation of amorphous‐silicon devices such as thin‐film transistors.

New high field‐effect mobility regimes of amorphous silicon alloy thin‐film transistor operation

A new theory of a‐Si thin‐film transistor (TFT) operation is presented. In addition to the below‐ and above‐threshold regimes described previously, it predicts two new regimes of operation which occur at very high densities of the induced charge in the a‐Si TFT channel. In a crystallinelike regime the free‐electron concentration exceeds the localized charge concentration at the a‐Si‐insulator interface. In a transitional regime (at lower densities of the induced charge) almost all localized states in the energy gap of amorphous silicon near the interface are filled. In the crystallinelike regime, the field‐effect mobility is close to the band mobility and the operation of an a‐Si TFT is truly similar to the operation of a crystalline field‐effect transistor. Our estimates show that the gate voltage necessary to achieve the crystallinelike regime is about 50 V for an a‐Si TFT with an insulator 1000 A thick and a relative permittivity of approximately 3.9.

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >

High-voltage amorphous silicon thin-film transistors

High-voltage MOSFETs have been fabricated in a large-area thin-film amorphous silicon technology. The transistors have an offset gate structure which allows them to operate at an excess of 400 V. Basic fabrication steps and structure are discussed. These transistors have a gate-controlled region in series with an offset region where the current is space charge limited. The I/sub D/-V/sub D/ characteristics exhibit a unique instability under drain voltage stress; there is a parallel shift in the I/sub D/ versus V/sub D/ characteristic to a higher V/sub D/. This instability arises from the creation of localized states in the a-Si during depletion. It is analyzed through experiment and two-dimensional simulation. Structural variations are described, including the application of a field plate, to stabilize transistor drive current. Reliability and process uniformity are discussed for arrays of transistors. An appropriate circuit simulation model is discussed. Operation of output drive circuits with high-voltage thin-film transistors (TFTs) is shown, and the application of these to an electrographic plotter is described. >