A.G. Lewis

Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation

The effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated. Based on the response of device parameters with the progress of hydrogenation, two types of defects can be distinguished from the difference in passivation rate. The threshold voltage and subthreshold slope, which are strongly influenced by the density of dangling bond midgap states, have a faster response to hydrogenation. The off-state leakage current and field-effect mobility, related to stain-bond tail states, respond more slowly to hydrogenation, with an onset period of approximately 4 to 12 h depending on the grain size. Since the larger-grain-size samples showed a longer onset period, the contribution of intragranular defects to the strain-bond tail states appears to be significant.<<ETX>>

Physical models for degradation effects in polysilicon thin-film transistors

Experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. A model is proposed to explain these effects whereby device performance degrades due to changes in the effective density of defect states in the material. Unlike single-crystal devices which degrade from hot-carrier effects, poly-Si TFTs are believed to degrade primarily due to the presence of high carrier densities in the channel. Good agreement between computer simulations of the device characteristics and experimental data ia demonstrated. It is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady-state conditions. >

Avalanche-induced effects in polysilicon thin-film transistors

A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices.<<ETX>>

Polysilicon TFT circuit design and performance

Both n- and p-channel polysilicon TFTs can be fabricated, allowing CMOS circuit techniques to be used. However, TFT characteristics are poor in comparison to conventional single-crystal MOSFETs, and relatively coarse design rules must be used to be compatible with processing on large-area glass plates. The authors examine these issues and describe the performance of a range of digital and analog circuit elements built using polysilicon TFTs. Digital circuit speeds in excess of 20 MHz are reported, along with operational amplifiers with over 80 dB of gain and more than 1-MHz unity-gain frequency. Several polysilicon TFT switched-capacitor circuits are also reported and shown to have adequate linearity, output swing, and settling time to form integrated data line drivers on an active-matrix liquid crystal display. >

A simpler 100-V polysilicon TFT with improved turn-on characteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process.<<ETX>>

Latchup performance of retrograde and conventional n-well CMOS technologies

The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+epitaxial material.

Physical mechanisms for short channel effects in polysilicon thin films transistors

It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias. The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes. At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts. Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage. When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves.<<ETX>>

Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors

An experimental study of mechanisms responsible for off-stage leakage currents in n- and p-channel poly-TFTs (thin-film transistors) is presented. Unlike turn-on characteristics, leakage currents are not symmetrical with respect to source-drain voltage polarity. The conduction mechanism in the off-state is consistent with the model of thermionic-field emission near the drain. The spatial and energetic distribution of trap-states in the drain depletion region affects the tunneling probability and causes device-to-device variation and the asymmetry in leakage current. The temperature dependence of the leakage current arises from the thermally activated carrier population at the energy state of the maximum tunneling probability. Cumulative leakage currents follow a Poisson-type log-normal distribution which can be significantly affected by processing control. Less than 10-fA/ mu m TFT width in leakage current and more than nine orders of magnitude on/off current ratio at 10-V drain bias were achieved in n-channel poly-TFTs.<<ETX>>

Device sensitivity of field-plated polysilicon high-voltage TFTs and their application to low-voltage operation

The device sensitivity to the offset length variations in the recently proposed field-plated (FP) polysilicon high-voltage thin-film transistor (HVTFT) has been studied. The device characteristics of the new FP-HVTFTs are found to be much more immune to misalignment errors; this is a very desirable feature, especially for large-area applications. FP-HVTFTs also exhibit lower leakage current than their conventional counterparts for up to 100-V operation. At typical low-voltage operation (e.g. 20 V), an improvement of about three orders of magnitude in the on/off current ratio can be readily achieved. These features, together with the simpler processing and improved turn-on characteristics reported earlier, make the FP-TFT a very promising device architecture for large-area microelectronics.<<ETX>>

Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs

The authors compare polysilicon n- and p-channel thin-film transistors (TFTs) which have been fabricated using either a low-temperature (<or=600 degrees C) glass compatible process or a high-temperature quartz-based technology. The former has the advantage of lower cost, while the latter offers better device performance. The significance of the differences in TFT characteristics between the two technologies is examined from the point of view of active matrix liquid crystal display design. It is shown that the low-temperature devices are adequate for implementing many of the peripheral circuits required by flat panel active matrix displays, and that simple CMOS designs remain attractive despite the relatively poor performance of the p-channel TFTs.<<ETX>>