Michael J. Alexander

Performance-oriented placement and routing for field-programmable gate arrays

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.

Placement and Routing for Performance-Oriented FPGA Layout

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

New Performance-Driven FPGA Routing Algorithms

Motivated by the goal of increasing the performance of FPGA-based designs, we propose effective Steiner and arborescence FPGA routing algorithms. Our graph-based Steiner tree constructions have provably-good performance bounds and outperform the best known ones in practice, while our arborescence heuristics produce routing solutions with optimal source-sink pathlengths at a reasonably low wirelength penalty. We have incorporated our algorithms into an actual FPGA router which routed a number of industrial circuits using channel widths considerably smaller than was previously possible.

Three-dimensional field-programmable gate arrays

Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption.

New performance-driven FPGA routing algorithms

Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions significantly outperform the best known ones and have provably good performance bounds. Our arborescence heuristics produce routing solutions with optimal source-sink pathlengths, and with wirelength on par with the best existing Steiner tree heuristics. We have incorporated these algorithms into an actual FPGA router, which routed a number of industrial circuits using channel width considerably smaller than is achievable by previous routers. Our routing results for both the 3000 and 4000-series Xilinx parts are currently the best known in the Literature.

Power optimization for FPGA look-up tables

We explore a new method for reducing power consumption/dissipation for FPGAs which is complementary to existing FPGA technology-mapping power-reduction techniques (e.g., [12]). Our approach is to reorder the input signals to the k-input look-up tables (k-LUTs) so that switching activity (and hence power dissipation) inside the look-up tables is minimized. We present algorithms which compute switching activity inside k-LUTs in optimal time. Our experimental results indicate that k-LUT input ordering is very e ective at reducing power dissipation within k-LUTs, providing savings of 26% on average [2] (savings vs. maximum are even greater).

Memory bandwidth optimizations for wide-bus machines

The authors describe and evaluate the effectiveness of some code improvement techniques that are designed to take advantage of wide-bus machines (WBMs): that is, a microprocessor with a memory bus width at least twice the size of the integer data type handled by the processor and assumed by the programmer. They discuss some compiler optimizations that take advantage of the increased bandwidth available from a wide bus. The investigations show that WBMs can expect reduction in memory bus cycles on the order of 5 to 15%. Using new code improvement algorithms designed to exploit the availability of a wide bus, the studies show that, for many memory-insensitive algorithms, it is possible to reduce the number of memory loads and stores by 30 to 40%.<<ETX>>

High-performance routing for field-programmable gate arrays

The advantages of field-programmable gate arrays (FPGAs) are sometimes eclipsed by a substantial performance penalty due to signal delay through the programmable routing resources. We propose a new FPGA routing construction that directly minimizes source-sink signal propagation delay based on a graph generalization of rectilinear Steiner arborescences (i.e. shortest-paths trees with minimum wirelength). Experimental results indicate that our new heuristic significantly reduces maximum source-to-sink pathlengths while using wirelength competitive with that of Steiner routing.<<ETX>>