Michael J. Uren

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Integrated micro-Raman/infrared thermography probe for monitoring of self-heating in AlGaN/GaN transistor structures

Self-heating in AlGaN/GaN device structures was probed using integrated micro-Raman/Infrared (IR) thermography. IR imaging provided large-area-overview temperature maps of powered devices. Micro-Raman spectroscopy was used to obtain high-spatial-resolution temperature profiles over the active area of the devices. Depth scans were performed to obtain temperature in the heat-sinking SiC substrate. Limitations in temperature and spatial resolution, and relative advantages of both techniques are discussed. Results are compared to three-dimensional finite-difference simulations

Thermal Boundary Resistance Between GaN and Substrate in AlGaN/GaN Electronic Devices

The influence of a thermal boundary resistance (TBR) on temperature distribution in ungated AlGaN/GaN field-effect devices was investigated using 3-D micro-Raman thermography. The temperature distribution in operating AlGaN/GaN devices on SiC, sapphire, and Si substrates was used to determine values for the TBR by comparing experimental results to finite-difference thermal simulations. While the measured TBR of about 3.3 x 10^-8 W^-1 ldr m² ldr K for devices on SiC and Si substrates has a sizeable effect on the self-heating in devices, the TBR of up to 1.2 x 10^-8 W^-1 ldr m² ldr K plays an insignificant role in devices on sapphire substrates due to the low thermal conductivity of the substrate. The determined effective TBR was found to increase with temperature at the GaN/SiC interface from 3.3 x 10^-8 W^-1 ldr m² ldr K at 150degC to 6.5 x 3.3 x 10^-8 W^-1 ldr m² ldr K at 275degC, respectively. The contribution of a low-thermal-conductivity GaN layer at the GaN/substrate interface toward the effective TBR in devices and its temperature dependence are also discussed.

Buffer Design to Minimize Current Collapse in GaN/AlGaN HFETs

The bulk trap-induced component of current collapse (CC) in GaN/AlGaN heterojunction field-effect transistors is studied in drift diffusion simulations, distinguishing between acceptor traps situated in the top and the bottom half of the bandgap, with Fe and C used as specific examples. It is shown that Fe doping results in an inherent but relatively minor contribution to dispersion under pulse conditions. This simulation is in reasonable quantitative agreement with double pulse experiments. Simulations using deep-level intrinsic growth defects produced a similar result. By contrast, carbon can induce a strong CC which is dependent on doping density. The difference is attributed to whether the trap levels, whether intrinsic or extrinsic dopants, result in a resistive n-type buffer or a p-type floating buffer with bias-dependent depletion regions. This insight provides a key design concept for compensation schemes needed to ensure semi-insulating buffer doping for either RF or power applications.

Channel Temperature Determination in High-Power AlGaN/GaN HFETs Using Electrical Methods and Raman Spectroscopy

Self-heating in AlGaN/GaN HFETs was investigated using electrical analysis and micro-Raman thermography. Two typically employed electrical methods were assessed to provide a simple means of extracting average channel temperatures in devices. To quantify the accuracy of these electrical temperature measurements, micro-Raman thermography was used to provide submicron resolution temperature information in the source-drain opening of the devices. We find that electrical methods significantly underestimate peak channel temperatures, due to the fact that electrical techniques measure an average temperature over the entire active device area. These results show that, although electrical techniques can be used to provide qualitative comparisons between different devices, they have challenges for the accurate estimation of peak channel temperatures. This needs to be taken into account for lifetime testing and reliability studies based on electrical temperature measurements.

Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-/spl mu/m SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage.

Intentionally Carbon-Doped AlGaN/GaN HEMTs: Necessity for Vertical Leakage Paths

Dynamic on-resistance (RON) in heavily carbon-doped AlGaN/GaN high electron mobility transistors is shown to be associated with the semi-insulating carbon-doped buffer region. Using transient substrate bias, differences in RON dispersion between transistors fabricated on nominally identical epilayer structures were found to be due to the band-to-band leakage resistance between the buffer and the 2-DEG. Contrary to normal expectations, suppression of dynamic RON dispersion in these devices requires a high density of active defects to increase reverse leakage current through the depletion region allowing the floating weakly p-type buffer to remain in equilibrium with the 2-DEG.

Iron-induced deep-level acceptor center in GaN/AlGaN high electron mobility transistors: Energy level and cross section

Dynamic transconductance dispersion measurements coupled with device physics simulations were used to study the deep level acceptor center in iron-doped AlGaN/GaN high electron mobility transistors (HEMT). From the extracted frequency dependent trap-conductance, an energy level 0.7 eV below the conduction band and a capture cross section of 10−13 cm2 were obtained. The approach presented in this work avoids the non-equilibrium electrical or optical techniques that have been used to date and extracts the device relevant trap characteristics in short channel AlGaN/GaN HEMTs. Quantitative prediction of the trap induced transconductance dispersion in HEMTs is demonstrated.

The effect of body contact series resistance on SOI CMOS amplifier stages

This paper examines some implications for analogue design of using body ties as a solution to the problem of floating body effects in partially-depleted (PD) SOI technologies. Measurements on H-gate body-tied structures in a 0.7-/spl mu/m SOI process indicate body-tie series resistances increasing into the M/spl Omega/ region. Both circuit simulation and measurement results reveal a delayed but sharper kink effect as this resistance increases. The consequences of this effect are shown in the context of a simple amplifier configuration, resulting in severe bias-dependent degradation in the small signal gain characteristics as the body-tie resistance enters the M/spl Omega/ region. It is deduced that imperfectly body tied devices may be worse for analogue design than using no body-tie at all.

On the link between electroluminescence, gate current leakage, and surface defects in AlGaN/GaN high electron mobility transistors upon off-state stress

The degradation of AlGaN/GaN high electron mobility transistors after off-state stress is studied by means of electroluminescence (EL) analysis, gate leakage current (Ig) monitoring, and atomic force microscopy (AFM) mapping of the semiconductor surface. It is found that the degradation of Ig upon stress is due to the combined effect of the individual defects underlying each of the EL spots, which contribute a few μA each to the total Ig. After removal of contacts and passivation, a direct one-to-one correspondence between EL spots and pits on the semiconductor surface is found. Reverse bias, conducting-tip AFM imaging showed that these surface pits do indeed act as leakage paths. Thus, the direct relationship between EL hot spots, surface pits, and gate current leakage is demonstrated. Discussion on the morphology of the surface pits and their possible origin is also provided.