Michael James Hartman

A synthesis environment for designing DSP systems

The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible architecture compilation environment), is to provide a set of algorithms that adequately support architecturally specific hardware synthesis for a class of DSP applications. They first identify the shortcomings of Parsifal, an earlier synthesis system, and discuss the requirements for FACE. They examine briefly the architectural issues. They then describe FACEs synthesis algorithms.<<ETX>>

Flexible module generation in the FACE design environment

The Flexible Architecture Compilation Environment (FACE) provides a common object-oriented representation for design information. A module-generation system built within the FACE environment that uses parameterized procedural module descriptions is discussed. These generators capture the knowledge of a designer and facilitate a high level of reuse of the modules and leaf cells. The system provides a general mechanism to parameterize design information and supports complex generators ranging from tiled structures to entire chips. This approach is applicable to many hardware architectures. Experience in the design of working VLSI chips is discussed.<<ETX>>

FACE Core Environment: The Model and its Application in CAE/CAD Tool Development

Many aspects of design automation software have similar requirements for representing, manipulating, and storing design information. The recognition of these common requirements in CAD tools, allows the Flexible Architecture Compilation Environments (FACE) Core Environment to provide a suite of high level tools for the CAD developer. The Core Environment software has been developed using object-oriented software technology, and may be readily adapted to specific applications. The focus of the core environment is to improve the productivity of CAD tool developers through better tool integration and a state-of-the-art software development environment. This Core Environment software has been used in the development of an integrated tool set covering algorithm specification, structural synthesis, and physical assembly of digital hardware systems. The focus of this paper is on the Core Environments organization and its use in application tool development.

Radioactive Source Estimation Using a System of Directional and Non-Directional Detectors

We derive source parameter estimation algorithms based on maximum likelihood estimation (MLE) for a system of non-directional (scintillator) and directional (CZT based Compton) radiation detectors. For multiple non-directional detectors, the joint likelihood of registered counts is maximized to estimate the source parameters. For directional detectors, the well-known List Mode Maximum Likelihood Expectation Maximization (MLEM) algorithm is extended to fuse information from multiple detectors and locate the source in Cartesian coordinates. We then develop multi-sensor fusion algorithms for a system of non-directional and directional detectors by combining MLE and MLEM algorithms. Results are presented which illustrate the behavior and performance of our proposed approaches.

Route based QoS and the biased early drop algorithm (BED)

DiffServ offers an attractive solution to quality of service (QoS) for mobile ad-hoc networks (MANET)s since the overhead of alternative flow based QoS metrics and signaling is not required. However, within prioritized classes and in the presence of dynamically forming bottlenecks, DiffServ can lead to brittle failure modes in which all flows are highly penalized and subsequently fail rather than maintaining some flows at required QoS levels for latency or packet loss. This problem is particularly difficult for UDP traffic, which does not respond to random early detection (RED) like throttling mechanisms in the presence of congestion. This paper proposes an augmentation of DiffServ QoS over MANET that utilizes metrics available through routing protocols to prevent, and resolve congestion. This is done in a manner that promotes maintenance of some high priority UDP (for example voice over IP) flows in the presence of bottlenecks. The biased early drop (BED) algorithm is introduced to maintain high continuity of UDP flows in the presence of congestion within the same class of service

Rapid prototyping using high density interconnects

This paper introduces the discretionary interconnect one-day electronic systems (DIODES) for the rapid prototyping of DSP electronic systems. DIODES merges silicon compiler and high-density interconnect technology with the goal of prototyping hardware systems as quickly as possible-within one day. Working from a high-level algorithmic description of a DSP algorithm, DIODES will determine which chips from an inventory of specially designed chips are needed to implement the design. These chips are then placed on a prepared substrate and routed together using computer controlled laser lithography to produce a hardware implementation of the design.<<ETX>>

Distributed optimization of Contention Windows in 802.11e MAC to provide QoS differentiation and maximize channel utilization

We propose a distributed algorithm for optimizing the Contention Windows in IEEE 802.11e based WLANs with the dual intention of providing fine-grained QoS and maximizing the channel utilization. The underlying concept behind the algorithm is modeling the network state as a function of MAC parameters and solving this analytical model constrained by the QoS requirements of multiple nodes. The main contribution of this paper is the completely distributed realization of this concept. The problem appears as a system of non-linear equations which is solved by an iterative gradient-based method. Distributed solution is achieved by first decoupling the equations and second by implicit message passing through local measurements. This allows local computation of partial differentials and residuals of the iterative process. Local measurements serve as inputs for the next iterative step and as natural feedback mechanism to handle dynamic channel conditions. Convergence of iterations is ensured through progressive target setting of QoS requirements. Extensive simulation results and a proof of concept with a test bed show that the algorithm achieves fine-grained QoS differentiation while minimizing delays, collisions and packet losses. As a result, when the network scales, the algorithm is shown to maximize the channel utilization and maintain a near optimal total throughput of the system. Finally, sub-minute convergence time makes the algorithm suitable for real-time flows.

A rapid-prototyping environment for digital-signal processors

A description is given of the Diodes system, a complete rapid prototyping, debugging, and test environment including both hardware and software, for the design of digital-signal-processing chips. The test circuitry in Diodes differs from that in many systems, including those based on boundary scan, by offering full-speed circuit testing and the observation of internal nodes during real time. Diodes also achieves nearly 100% fault coverage because chips are composed of numerous chunks, each of which is tested exhaustively. The discussion covers the high-density interconnection technology and the concepts on which Diodes is based, two types of chips that have been designed, fabricated, and tested for Diodes: module assembly and fabrication; synthesis software; on-chip testing; Diodes test circuitry; test modes; and hardware and software debugging. Diodes is compared with other testing approaches and other rapid prototyping systems.<<ETX>>

A synthesis, test and debug environment for rapid prototyping of DSP designs

Recently, considerable progress has been made in the design of digital signal processing (DSP) integrated circuits and systems. In order to address the need for rapid and economical production and testing of hardware prototypes, a hardware and software system called DIODES is being developed for the rapid prototyping, testing and debugging of DSP designs. DIODES will allow the user to design a DSP system, have it partitioned into predefined function blocks, have it assembled using advanced packing technology and then thoroughly test and debug the design both stand-alone and in a larger electronic system environment. This paper gives an overview of the whole system focussing particularly on the debugging hardware and software support environment. The algorithmic description is translated by the DIODES synthesis software into a structural specification suitable for High-Density Interconnect (HDI) fabrication. The synthesis process includes the insertion of test capabilities into the hardware to allow for debugging the design. The rapid turnaround of HDI fabrication means that the user can have a prototype DIODES module in hand ready for testing within at most a day or two, and at moderate cost.<<ETX>>

An Abstract Internet Topology Model for Simulating Peer-to-Peer Content Distribution

In recent years, many researchers have run simulations of the Internet. The Internets inherent heterogeneity and constantly changing nature make it difficult to construct a realistic, yet computationally feasible model. In the construction of any model, one must take into consideration flexibility, accuracy, required resources, execution time, and realism. In this paper, we discuss the methodology and creation of a model used to simulate Internet content distribution, and the rationale used behind its design. In particular, we are interested in modeling the in-home consumer broadband Internet, while preserving geographical market relationships. In our performance study, our simulations experience tremendous speedups, and require a fraction of the memory of other models, without sacrificing the accuracy of our findings. Specifically, our piece-level model achieves the accuracy of a packet-level model, while requiring the processing of 40 times fewer events.