Michael K. Cheng

LDPC Codes for Memory Systems with Scrubbing

In space, radiation particles can introduce temporary or permanent errors in memory systems. To protect against potential memory faults, either thick shielding or error correcting codes (ECC) are used. Thick shielding translates into increased mass and conventional ECCs designed for memories are typically capable of only correcting a single error and detecting a double error. Decoding is usually performed through hard-decisions where bits are treated as either correct or flipped in polarity. In this work, we demonstrate that low-density parity-check (LDPC) codes that are already prevalent in many communication applications can also be used to protect memories in space. We develop a channel that models memory error events in a space radiation environment. We describe how to compute soft symbol reliabilities on our channel and compare the performance of softdecision decoding LDPC codes against conventional hard-decision decoding of Reed-Solomon (RS) codes and Bose-Chaudhuri- Hoquenghem (BCH) codes for a specific memory structure.

An interleaver implementation for the serially concatenated pulse-position modulation decoder

We describe novel interleaver and deinterleaver architectures that support bandwidth efficient memory access for decoders of turbo-like codes that are used in conjunction with high order modulations. The presentation focuses on a decoder for serially concatenated pulse-position modulation (SCPPM), which is a forward-error-correction code designed by NASA to support laser communications from Mars at mega-bits-per-second (Mbps) rates. For 64-ary PPM, the new architectures effectively triple the fan-in of the interleaver and fan-out of the deinterleaver, enabling parallelization that doubles the overall throughput. The techniques described here can be readily modified for other PPM orders

Scrubbing with partial side information for radiation-tolerant memory

Memory systems used in space applications suffer from radiation-induced errors, either temporary upsets (soft errors) or permanent defects (hard errors or stuck-at errors). Scrubbing is a method to protect memory contents by periodically decoding the stored data to correct those soft and stuck-at errors then rewriting the corrected data back into memory. However, defective cells will remain and accumulate over time. Conventional coding disregards defective cells, however this may be inefficient for memory protection in space. In this study, alternative coding schemes for scrubbing are investigated, where the channel model depends on the cell states, defective or not, and the encoder uses channel state information (CSI) or side information. At every scrubbing, the error correcting code (ECC) decoder provides partial CSI back to the encoder and the encoder uses the CSI to improve the performance of memory systems with scrubbing. Information theoretic limits of the channel with partial CSI are investigated and several coding schemes are introduced to mitigate the effects of defective cells, particularly those caused by stuck-at defects. In addition, coding schemes with partial CSI are concatenated with binary Bose-Chaudhuri-Hocquenghem (BCH) codes to protect memory contents from both soft and stuck-at errors in space radiation environments. Numerical simulation results show that scrubbing with partial CSI improves reliability over the state-agnostic approaches.

Palomar Receive Terminal (PRT) for the Mars Laser Communication Demonstration (MLCD) Project

Significant technological advances were made toward utilizing the Hale telescope for receiving the faint laser communication signals transmitted from an optical transceiver on a spacecraft orbiting Mars. The so-called Palomar receive terminal design, which would have supported nominal downlink data rates of 1-30 Mbps, is described. Testing to validate technologies for near-Sun (3deg from edge of solar disc) daytime operations is also discussed. Finally, a laboratory end-to-end link utilizing a 64-ary pulse-position modulated photon-counting receiver and decoder that achieved predicted near-capacity (within 1.4 dB) performance is described.

SAT05-4: Implementation of a Coded Modulation for Deep Space Optical Communications

We present an efficient implementation of a coded modulation for the deep space optical channel. NASA designed this so called serially concatenated pulse position modulation (SCPPM) code to provide an optical link that can operate within one dB signal energy of the Shannon capacity during a nominal mission condition from Mars. Here, we describe some of the challenges in realizing the SCPPM decoder on a field-programmable gate array (FPGA). Through various architectural optimizations, we achieve a 6 Mbps decoder on a single FPGA. Moreover, we demonstrate that it is possible to communicate reliably on an efficient bits-per-photon count in an end-to-end SCPPM coded system.

Jitter-Induced Symbol Slip Rates in Next-Generation Ground Segment Receivers

NASA is in the process of modernizing its communications infrastructure to accompany the development of a Crew Exploration Vehicle (CEV) to replace the Space Shuttle. With this effort comes the opportunity to infuse more advanced coded modulation techniques, including low-density parity-check (LDPC) codes that offer greater coding gains than the current capability. However, in order to take full advantage of these codes, the ground segment receiver synchronization loops must be able to operate at a lower signal-to-noise ratio (SNR) than supported by equipment currently in use. At low SNR, the receiver symbol synchronization loop will be increasingly sensitive to transmitter timing jitter. Excessive timing jitter can cause bit slips in the receiver synchronization loop, which will in turn cause frame losses and potentially lead to receiver and/or decoder loss-of-lock. Therefore, it is necessary to investigate what symbol timing jitter requirements on the satellite transmitter are needed to support the next generation of NASA coded modulation techniques. The work presented here is based on a series of receiver measurements at the Electronics Systems Test Laboratory (ESTL) in Johnson Space Center (JSC), coupled with empirical observations made on the performance of the symbol synchronizer loop. Measurements of ground segment receiver sensitivity to transmitter bit jitter were conducted at ESTL using a satellite transponder and two different commercial off-the-shelf (COTS) Staggered QPSK (SQPSK) receivers. The symbol synchronizer loop transfer functions were characterized for each COTS receiver. Symbol timing jitter was introduced at the transmitter. Effects of sinusoidal (tone) jitter on symbol error rate (SER) degradation and symbol slip probability were measured. These measurements were used to define regions of sensitivity to phase, frequency, and cycle-to-cycle jitter characterizations. An assortment of other band-limited jitter waveforms was then applied within each region to identify peak or root-mean-square measures as a basis for comparability. Results from the ESTL test and analysis indicate that the receiver symbol synchronization loop is more sensitive to certain types of symbol jitter and jitter frequencies, depending on the selection of the loop filter and damping ratio. It is also shown that the target symbol slip probability of less than 10 -12 can be achieved for E s /N 0 < -0.8 dB, provided that the timing jitter does not exceed certain limits and through proper selection of receiver synchronization loop parameters. A symbol timing jitter mask derived from the experimental data is presented, which would allow for less than 0.1 dB degradation in SER performance at low E s /N 0 due to transmit symbol timing jitter.

A multibit-per-cell memory model and nonbinary LDPC codes

Protecting nonvolatile memory systems in harsh radiation environments encountered in space missions is important and error correcting schemes can extend the lifetime of those memory systems. For example, recent research has shown that LDPC codes can extend the lifetime of nonvolatile memory under space radiation environment more than Bose-Chaudhuri-Hocquenghem (BCH) or Reed-Solomon (RS) codes at fixed codeword error rates. However, conventional memory models assume that bit errors are independent, but multibit errors were reported in satellite experiments. Moreover, memory feature sizes are shrinking and multibit-per-cell structures are becoming standard so radiation will increasingly lead to multibit errors. For these reasons, we can expect that the bit errors in memory systems will be correlated. In this work, we develop a mathematical multibit-per-cell memory model under a radiation environment. In this memory model, bit errors are correlated and the probability of errors depends on radiation parameters and time. For correlated bit errors, nonbinary codes can be more effective than binary codes. We will demonstrate that nonbinary LDPC code can outperform conventional BCH and RS codes in a correlated multibit error environment.

Integrated Performance of Next Generation High Data Rate Receiver and AR4JA LDPC Codec for Space Communications

Low-density parity-check (LDPC) codes are the state-of-the-art in forward error correction (FEC) technology that exhibits capacity approaching performance. The Jet Propulsion Laboratory (JPL) has designed a family of LDPC codes that are similar in structure and therefore, leads to a single decoder implementation. The Accumulate-Repeat-by-4-Jagged- Accumulate (AR4JA) code design offers a family of codes with rates 1/2, 2/3, 4/5 and lengths 1024, 4096, 16384 information bits. Performance is less than one dB from capacity for all combinations.Integrating a stand-alone LDPC decoder with a commercial-off-the-shelf (COTS) receiver faces additional challenges than building a single receiver-decoder unit from scratch. In this work, we outline the issues and show that these additional challenges can be over-come by simple solutions. To demonstrate that an LDPC decoder can be made to work seamlessly with a COTS receiver, we interface an AR4JA LDPC decoder developed on a field-programmable gate array (FPGA) with a modern high data rate receiver and mea- sure the combined receiver-decoder performance. Through optimizations that include an improved frame synchronizer and different soft-symbol scaling algorithms, we show that a combined implementation loss of less than one dB is possible and therefore, most of the coding gain evidence in theory can also be obtained in practice. Our techniques can benefit any modem that utilizes an advanced FEC code.

Undetected Errors in Quasi-Cyclic LDPC Codes Caused by Receiver Symbol Slips

Low-density parity-check (LDPC) codes are capacity-approaching forward error correction codes that operate at signal-to-noise ratio (SNR) decoding thresholds very near to the capacity limits. Receivers designed for less optimal codes might not function smoothly at the lower values of SNR where LDPC codes can operate. In particular, an artifact of low-SNR receiver operation is the increased probability of symbol slips. Receiver synchronization errors resulting from symbol insertions or deletions can cause unexpected decoder problems, especially for an LDPC code with a quasi-cyclic construction. In this paper we analyze the theoretical basis for symbol slips to cause undetected errors with quasi-cyclic codes, and we demonstrate these effects via simulations. We also examine several no-cost to low-cost solutions that can mitigate these effects.