Michael Kubis

Holistic optimization architecture enabling sub-14-nm projection lithography

Abstract. Parallel with the introduction of EUV lithography, immersion lithography is being extended to the 14- and 10-nm node, and the lithography performance requirements need to be tightened further to enable this shrink. Next to generic scanner system improvements, application-specific solutions are needed to follow the requirements for critical dimension (CD) control and overlay. The application-specific solutions need a holistic optimization approach for the scanner, the mask, and the patterning process. We will describe the holistic lithography systems architecture that enables dynamic use of high-order scanner optimization based on advanced actuators of projection lens and scanning stages. Next to the scanner system, key components of this architecture are an angle-resolved scatterometer to measure CD, overlay, and focus, and an off-tool computation server to calculate application-specific recipes for the scanner. Based on real production wafer data, we will show the benefit for CD control, focus control, and overlay control, and demonstrate lithography performance levels required for 14- and 10-nm node production.

YieldStar: a new metrology platform for advanced lithography control

As leading edge lithography is moving to 2x-nm design rules, lithography control complements resolution as one of the main drivers and enablers to meet the very stringent overlay, focus and CD requirements. As part of ASMLs holistic lithography roadmap, ASML is developing several application-specific optimization and control applications, such as LithoTuner Pattern Matcher and BaseLiner. These applications are all explicitly designed to improve the scanner process window (overlay, focus, CDU and matching). All these applications have in common that they require vast amounts of precise, accurate and process robust wafer data (either taken on product stacks or on so-called monitor wafers). To provide such essential data in a cost-effective manner, ASML developed a metrology platform, called YieldStar. This platform is based on an angle-resolved high-NA scatterometer. It is versatile, as YieldStars sensor can measure overlay, CD and focus in a single measurement. Thanks to its high speed, large amounts of measurements can be quickly collected. In this paper the latest generation YieldStar is presented, the so-called 200 platform. This YieldStar 200 can be used in a stand-alone configuration (S-200) or as an integrated module in a lithography track (T-200). First overlay results show good TMU results without comprising speed. Furthermore, data is shown that demonstrate YieldStars capability to reconstruct 3D CD patterns as well.

Integrated scatterometry for tight overlay and CD control to enable 20-nm node wafer manufacturing.

The overlay, CDU and focus requirements for the 20nm node can only be met using a holistic lithography approach whereby full use is made of high-order, field-by-field, scanner correction capabilities. An essential element in this approach is a fast, precise and accurate in-line metrology sensor, capable to measure on product. The capabilities of the metrology sensor as well as the impact on overlay, CD and focus will be shared in this paper.

Evaluation of a novel ultra small target technology supporting on- product overlay measurements

Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay metrology.

Combined overlay, focus and CD metrology for leading edge lithography

As leading edge lithography moves to 22-nm design rules, low k1 technologies like double patterning are the new resolution enablers, and system control and setup are the new drivers to meet remarkably tight process requirements. The way of thinking and executing setup and control of lithography scanners is changing in four ways. First, unusually tight process tolerances call for very dense sampling [1], which in effect means measurements at high throughput combined with high order modeling and corrections to compensate for wafer spatial fingerprint. Second, complex interactions between scanner and process no longer allow separation of error sources through traditional metrology approaches, which are based on using one set of metrology tools and methods for setup and another for scanner performance control. Moreover, setup and control of overlay is done independently from CD uniformity, which in effect leads to independent and conflicting adjustments for the scanner. Third, traditional CD setup and control is based on the focus and dose calculated from their CD response and not from measurement of their effect on pattern profile, which allows a clean and orthogonal de-convolution of focus and dose variations across the wafer. Fourth, scanner setup and control has to take into consideration the final goal of lithography, which is the accurate printing of a complex pattern describing a real device layout. To this end we introduce a new setup and control metrology step: measuring-to-match scanner 1D and 2D proximity. In this paper we will describe the strategy for setup and control of overlay, focus, CD and proximity based on the YieldStarTM metrology tool and present the resulting performance. YieldStar-200 is a new, high throughput metrology tool based on a high numerical aperture scatterometer concept. The tool can be used stand-alone as well as integrated in a processing track. It is suitable for determining process offsets in X,Y and Z directions through Overlay and Focus measurements respectively. In addition CD profile information can be measured enabling proximity matching applications. By using a technique [2][3][4] to de-convolve dose and focus based on the profile measurement of a well-characterized process monitor target, we show that the dose and focus signature of a high NA 193nm immersion scanner can be effectively measured and corrected. A similar approach was also taken to address overlay errors using the diffraction based overlay capability [5] of the same metrology tool. We demonstrate the advantage of having a single metrology tool solution, which enables us to reduce dose, focus and overlay variability to their minimum non-correctable signatures. This technique makes use of the high accuracy and repeatability of the YieldStar tool and provides a common reference of scanner setup and user process. Using ASMLs YieldStar in combination with ASML scanners, and control solutions allows for a direct link from the metrology tool to the system settings, ensuring that the appropriate system settings can be easily and directly updated.

High order field-to-field corrections for imaging and overlay to achieve sub 20-nm lithography requirements

Immersion lithography is being extended to the 20-nm and 14-nm node and the lithography performance requirements need to be tightened further to enable this shrink. In this paper we present an integral method to enable high-order fieldto- field corrections for both imaging and overlay, and we show that this method improves the performance with 20% - 50%. The lithography architecture we build for these higher order corrections connects the dynamic scanner actuators with the angle resolved scatterometer via a separate application server. Improvements of CD uniformity are based on enabling the use of freeform intra-field dose actuator and field-to-field control of focus. The feedback control loop uses CD and focus targets placed on the production mask. For the overlay metrology we use small in-die diffraction based overlay targets. Improvements of overlay are based on using the high order intra-field correction actuators on a field-tofield basis. We use this to reduce the machine matching error, extending the heating control and extending the correction capability for process induced errors.

On-product overlay enhancement using advanced litho-cluster control based on integrated metrology, ultra-small DBO targets and novel corrections

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

Overlay improvements using a real time machine learning algorithm

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system’s sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Integrated approach to improving local CD uniformity in EUV patterning

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn’t be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.