Guo-Tsai Huang

Evaluation of a novel ultra small target technology supporting on- product overlay measurements

Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay metrology.

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.

Accuracy of diffraction-based and image-based overlay

There is no overlay standard in the world. For critical dimension (CD), we may use the VLSI standard or programmed pitch offsets to determine the CD accuracy or CD sensitivity. Programmed overlay offsets can provide relatively accurate sub-nanometer level overlay splits but it is only on a single layer and does not contain layer-to-layer process variations. The splits of scanner magnification can check the trend of overlay sensitivity but it cannot provide the exact value of overlay offsets. Transmission electron microscopes (TEM) can be used as a final overly error verification tool. However, TEM sample preparation for after-development-inspection (ADI) will introduce even more sample distortion errors. Therefore, unlike CD metrology, there is no clean and systematic way to verify the accuracy of overlay metrology. These technical barriers necessitate matching diffraction-based overlay and image-based overlay, especially for sub-nanometer point-to-point matching requirement. In this paper, we compare the correlation of ADI to after-etch-inspection (AEI) by using image-based box-in-box overlay measurement and diffraction-based overlay measurement on the same wafer. The ADI-to-AEI overlay data consistency plays a key role for lithography overlay APC success and AEI overlay should be treated as the final standard for overlay accuracy. We found that process-induced asymmetric profiles of overlay marks will lead to ADI-to-AEI overlay bias. This bias is proportional to the degree of profile asymmetry and different color/wavelength have different sensitivity to this ADI-to-AEI bias. Our experimental results show that the ADI-to-AEI overlay data bias can indeed be significantly improved by selecting the color/wavelength with minimum sensitivity to the asymmetry profile. These results make us believe that overlay metrology recipe setup is quite critical no matter for image-based overlay or diffraction-based overlay. Otherwise, problematic overlay data will be taken into APC feedback loop and lead to wrong overlay correction.

On-product overlay enhancement using advanced litho-cluster control based on integrated metrology, ultra-small DBO targets and novel corrections

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

A sophisticated metrology solution for advanced lithography: addressing the most stringent needs of today as well as future lithography

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level [4]. Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform. This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus) and product wafer applications.

A paradigm shift in scatterometry-based metrology solution addressing the most stringent needs of today as well as future lithography

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput). Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications. Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.

Advanced litho-cluster control via integrated in-chip metrology

The high-end semiconductor lithography requirements for overlay and focus control in near-future ITRS nodes are at subnanometer level. This development is extremely challenging for the metrology precision and accuracy, as scaling down to the sub-angstrom level is required for this. On top of the extreme metrology requirements, direct feed-back control of the lithographic steps is needed to meet the future node requirements. Integrated metrology with in-chip measurements, advanced sampling and control-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

Mask registration impact on intrafield on-wafer overlay performance

Improved overlay performance is one of the critical elements in enabling the continuing advancement of the semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay and point out the importance of high density sampling as well as the potential for improved mask qualification and disposition.

Sub-nanometer in-die overlay metrology: measurement and simulation at the edge of finiteness

The target size reduction for overlay metrology is driven by the optimization of the device area. Furthermore, for the future semiconductor nodes accurate metrology on the order of 0.2 nm is necessary locally in the device area, requiring small in-die targets that fit within the product structures on the wafer. In this, the diffraction-based overlay metrology using optical scatterometry is challenged to extreme limits. The small grating cannot be considered as an infinitely repeating line-space structure with a sharply peaked spectrum, however a continuous spectrum is observed. Also, metrology proximity effects due to the environment near the metrology target need to be taken into account. On the one hand, this sets strict design and assembly rules of the metrology sensor. On the other hand, the optical ray-based analysis is extended to wave-based analysis to capture the full extent of the overlay application and sensor. In this publication, the challenges of sub-nanometer in-die overlay metrology are addressed, including measurements and simulations.

Multi-wavelength approach towards on-product overlay accuracy and robustness

Success of diffraction-based overlay (DBO) technique1,4,5 in the industry is not just for its good precision and low toolinduced shift, but also for the measurement accuracy2 and robustness that DBO can provide. Significant efforts are put in to capitalize on the potential that DBO has to address measurement accuracy and robustness. Introduction of many measurement wavelength choices (continuous wavelength) in DBO is one of the key new capabilities in this area. Along with the continuous choice of wavelengths, the algorithms (fueled by swing-curve physics) on how to use these wavelengths are of high importance for a robust recipe setup that can avoid the impact from process stack variations (symmetric as well as asymmetric). All these are discussed. Moreover, another aspect of boosting measurement accuracy and robustness is discussed that deploys the capability to combine overlay measurement data from multiple wavelength measurements. The goal is to provide a method to make overlay measurements immune from process stack variations and also to report health KPIs for every measurement. By combining measurements from multiple wavelengths, a final overlay measurement is generated. The results show a significant benefit in accuracy and robustness against process stack variation. These results are supported by both measurement data as well as simulation from many product stacks.