Michael L. Bushneil

Quadratic 0-1 Programming

Once the test generation problem has been formulated as an optimization problem on a neural network, several methods can be used to find the minimum of the energy function.

Test Generation Reformulated

We formulate the test generation problem as an optimization problem such that the desired optima are the test vectors for some target fault. This formulation captures three necessary and sufficient conditions that any set of signal values must satisfy to be a test. First, the set of values must be consistent with each gate’s function in the circuit. Second, the signal in the fault-free and faulty circuits at the fault site must assume opposite values (e.g., 0 and 1 respectively, for a s-a-1 fault). Third, for the same primary input vector, the fault-free and faulty circuits should produce different output values.

Neural Modeling for Digital Circuits

We can relate the input and output signal states of a logic gate through an energy function, defined over a network of neurons, such that the minimum- energy states correspond to the gate’s function. Similarly, the function of an entire circuit, consisting of any arbitrary interconnections of logic gates, can be expressed by a single energy function. Several reasons motivate this new approach. First, since the function of the circuit is captured in the energy expression, mathematical techniques such as non-linear programming can be used to solve test generation and other design problems. Second, graph-theoretic techniques can be applied to the neural network graph to accelerate the minimization of the energy function. Third, the non-causal form of this model allows the use of parallel processing for compute-intensive design automation tasks.

Logic Circuits and Testing

This chapter is a tutorial on logic circuit modeling, fault modeling and test generation [5]. Concepts of testing, as used in later chapters, are briefly reviewed. Readers having a basic understanding of these concepts may choose to skip this chapter.

Polynomial-time Testability

The problem of detecting a fault in a general combinational circuit is NP-complete [5] and it is unlikely that a polynomial time algorithm exists for solving it. The non-polynomial time complexity here refers to the worst-case effort of test generation in a circuit. Consequently, it is of interest to identify circuits for which a polynomial time fault detection algorithm exists. The number of primary inputs and the number of signals in the digital circuit are generally considered as the the input size for the fault detection problem.

Parallel Processing Preliminaries

Parallel processing is viewed as a way to overcome the limitations of single-processor systems. Two distinct styles of parallel computing are emerging. One method uses an array of cooperating processors, suitably synchronized by a clocking mechanism, such that each develops a part of the solution that it shares with other neighbors. The other method uses neural networks and is a radically different way of parallel processing. These networks are interconnections of analog computing elements that cooperatively evolve toward a configuration, interpreted as a solution to the problem. There is no clock and the time evolution of the network follows a trajectory described by a set of differential equations. Such computation, that will perhaps mimic the behavior of the human brain, may be the way of the future [13].

Simulated Neural Networks

Large scale implementations of neural networks arc presently not available. However, serial and parallel computers have been used to simulate neural networks [2, 5]. We describe algorithms for simulating the neural network on a serial computer and discuss possible implementations of these algorithms on parallel computers. Chapter 8 discusses test generation on a commercial hardware accelerator for neural network simulatioa

Special Cases of Hard Problems

It is unlikely that a polynomial time algorithm exists for finding exact solutions of all instances of an NP-complete problem [8]. Heuristics are generally used to find reasonably good solutions. However, there may be several instances of the problem for which exact solutions can be found quickly (i.e., in polynomial time).

Solving Graph Problems

In this chapter, we present a VLSI solution of a classical graph problem, the independent set problem. This problem occurs in many applications including computer-aided design. Our solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the neural network model of the logic circuit. Each input vector provides one solution of the independent set problem. The independent set consists of only vertices with true encoding. This new methodology has the potential of solving the problem in real time if programmable logic is used [8].

Transitive Closure And Testing

In previous chapters, we used transitive closure to speed up the energy minimization algorithms. Now we present a test generation algorithm entirely based on transitive closure. A test is obtained by determining signal values that satisfy a Boolean expression constructed from the circuit netlist and the fault. The algorithm is a sequence of two main steps that are repeatedly executed: transitive closure computation and decision-making. The transitive closure computation determines all logical consequences of any partial set of signal assignments. To compute the transitive closure of the circuit, we construct an implication graph whose vertices are labeled as the true and false states of all signals. A directed edge (x, y) in this graph represents the controlling influence of the true state of signal x on the true state of signal y. The signals x and y are connected through a wire or a gate in the circuit. Since the implication graph only includes pairwise (or binary) relations, it is a partial representation of the netlist. The transitive closure of the implication graph contains pairwise logical relationships among all signals. When signal relationships describing fault activation and path sensitization are included, transitive closure determines signal fixations and logical contradictions that directly identify many redundancies. Implication, unique path sensitization, static and dynamic learning, sensitization of physical and logical dominators and other techniques that are useful in determining necessary signal assignments are implicit in the process. If signals thus determined satisfy the Boolean formula, we have a test. Otherwise, we use the decision-making step, fix an unassigned signal, and update the transitive closure to determine all logical consequences of this decision. Since computation of transitive closure is as easily parallelizable as matrix multiplication, our algorithm is suitable for execution on a multiprocessor system.