Michael M. C. Merlin

High-Frequency Operation of a DC/AC/DC System for HVDC Applications

Voltage ratings for HVdc point-to-point connections are not standardized and tend to depend on the latest available cable technology. DC/DC conversion at HV is required for interconnection of such HVdc schemes as well as to interface dc wind farms. Modular multilevel voltage source converters (VSCs), such as the modular multilevel converter (MMC) or the alternate arm converter (AAC), have been shown to incur significantly lower switching losses than previous two- or three-level VSCs. This paper presents a dc/ac/dc system using a transformer coupling two modular multilevel VSCs. In such a system, the capacitors occupy a large fraction of the volume of the cells but a significant reduction in volume can be achieved by raising the ac frequency. Using high frequency can also bring benefits to other passive components such as the transformer but also results in higher switching losses due to the higher number of waveform steps per second. This leads to a tradeoff between volume and losses which has been explored in this study and verified by simulation results with a transistor level model of 30-MW case study. The outcome of the study shows that a frequency of 350 Hz provides a significant improvement in volume but also a penalty in losses compared to 50 Hz.

The Alternate Arm Converter: A New Hybrid Multilevel Converter With DC-Fault Blocking Capability

This paper explains the working principles, supported by simulation results, of a new converter topology intended for HVDC applications, called the alternate arm converter (AAC). It is a hybrid between the modular multilevel converter, because of the presence of H-bridge cells, and the two-level converter, in the form of director switches in each arm. This converter is able to generate a multilevel ac voltage and since its stacks of cells consist of H-bridge cells instead of half-bridge cells, they are able to generate higher ac voltage than the dc terminal voltage. This allows the AAC to operate at an optimal point, called the “sweet spot,” where the ac and dc energy flows equal. The director switches in the AAC are responsible for alternating the conduction period of each arm, leading to a significant reduction in the number of cells in the stacks. Furthermore, the AAC can keep control of the current in the phase reactor even in case of a dc-side fault and support the ac grid, through a STATCOM mode. Simulation results and loss calculations are presented in this paper in order to support the claimed features of the AAC.

Power loss and thermal characterization of IGBT modules in the Alternate Arm converter

Power losses in high power HVDC converters are dominated by those that occur within the power electronic devices. This power loss is dissipated as heat at the junction of semiconductor devices. The cooling system ensures that the generated heat is evacuated outside the converter station but temperature management remains critical for the lifetime of the semiconductor devices. This paper presents the results of a study on the temperature profile of the different switches inside a multilevel converter. The steady state junction temperatures are observed through the simulation of a 20 MW Alternate Arm Converter using 1.2kA 3.3 kV IGBT modules. A comparison of the Alternate Arm Converter is made against the case of both the half-bridge and full-bridge Modular Multilevel Converter topologies. Furthermore, the concept of varying the duty-cycle of the two alternative zero-voltage states of the H-bridge modules is introduced. Simulation results demonstrate that it can change the balance of electrical and thermal stress between the two top switches and the two bottom switches of a full-bridge cell.

Reduced Dynamic Model of The Alternate Arm Converter

The Alternate Arm Converter (AAC) is a hybrid HVDC converter that maintains low power losses while protecting against DC-side faults. This paper shows the development of a Reduced Dynamic Model (RDM) of the AAC which enables time efficient system level modelling of multi-converter HVDC systems. The methodology and equations to develop the RDM are described. The RDM is then compared directly to a full switching model of the AAC, where the accuracy and the computation times are measured. The RDM is observed to simulate almost 20 times faster than the full dynamic model. The RDM is then evaluated under normal and abnormal operating conditions using a point to point HVDC model while maintaining a good level of accuracy.

Operation of HVDC Modular Multilevel Converters under DC pole imbalances

Operation of HVDC converters under HVDC pole voltage imbalances is analysed. Asymmetrical HVDC pole current injection is achieved by directing current to the ground return path through a device installed in the AC side of the converter. Several operation modes, including asymmetric monopole, are presented and their sizing requirements are discussed.

Lab-scale experimental multilevel modular HVDC converter with temperature controlled cells

It is important to be able to produce representative experimental results when researching HVDC grids and converters. This paper reports on a lab-scale multi-level converter build. The converter was built with a large number of cells to enable experiments with cell balancing effects and with temperature control to investigate thermal effects and appropriate responses. The converter is able to behave as both a traditional MMC (or CTLC which is functionally similar) and as the newer AAC converter. Results are presented that show the converter is able to charge up from the DC bus and is able to function well with both static and changing power references.

Choice of AC operating voltage in HV DC/AC/DC system

Demand for DC/DC conversion in HV applications is expected to rise because of the increasing number of HVDC links using different DC voltage levels. This paper presents a DC/AC/DC system consisting of two VSCs connected through an inductor. The two VSCs are Alternate Arm Converters (AAC). Since the two AACs share the same AC voltage level, they cannot be operated at their respective “sweet-spots” at the same time. This results in an energy drift in the valves which is tackled by additional balancing currents. However, the choice of the AC voltage level remains critical as it determines the required amount of balancing current, the number of devices and the cell topology, influencing greatly the total efficiency and volume of the obtained DC/DC converter. A study on a scale-down converter highlights the trade-offs affecting the AC voltage choice.

A high density converter for mid feeder voltage regulation of low voltage distribution feeders

The paper proposes a power electronic converter to solve the problem of voltage constrained Low Voltage (LV) distribution cables where spare thermal capacity is available. The converter utilises a high frequency AC link inverter as part of a shunt/series topology similar to that of a Unified Power Flow Controller (UPFC). The design of the converter is described with reference to the criteria that it should be as compact as possible, hence large 50Hz transformers are rejected in favour of a small high frequency transformer. A simulation is developed and the performance of the converter analysed with respect to efficiency. It is concluded that a device such as that described could form the basis for a power electronic solution to the problem of voltage constrained feeders on a low voltage distribution network.

Dimensioning and Modulation Index Selection for the Hybrid Modular Multilevel Converter

A hybrid modular multilevel converter, comprising a mixture of full-bridge and half-bridge submodules, provides tolerance to dc faults without compromising the efficiency of the converter to a large extent. The inclusion of full bridges creates a new freedom over the choice of ratio of ac-to-dc voltage at which the converter is operated, with resulting impact on the converters internal voltage, current, and energy deviation waveforms, all of which impact the design of the converter. A design method accounting for this and allowing the required level of derating of nominal submodule voltage and uprating of stack voltage capability to ensure correct operation at the extremes of the operating envelope is presented. A mechanism is identified for balancing the peak voltage that the full-bridge and half-bridge submodules experience over a cycle. Comparisons are made between converters designed to block dc-side faults and converters that also add STATCOM capability. Results indicate that operating at a modulation index of 1.2 gives a good compromise between reduced power losses and additional required submodules and semiconductor devices in the converter. The design method is verified against simulation results, and the operation of the converter at the proposed modulation index is demonstrated at the laboratory scale.

Thyristor-Bypassed Submodule Power-Groups for Achieving High-Efficiency, DC Fault Tolerant Multilevel VSCs

Achieving dc fault tolerance in modular multilevel converters requires the use of a significant number of submodules (SMs) that are capable of generating a negative voltage. This results in an increase in the number of semiconductor devices in the current path, increasing converter conduction losses. This paper introduces a thyristor augmented multilevel structure called a Power-Group (PG), which replaces the stacks of SMs in modular converters. Each PG is formed out of a series stack of SMs with a parallel force-commutated thyristor branch, which is used during normal operation as a low loss bypass path in order to achieve significant reduction in overall losses. The PG also offers negative voltage capability and so can be used to construct high-efficiency dc fault tolerant converters. Methods of achieving the turn-on and turn-off of the thyristors by using voltages generated by the parallel stack of SMs within each PG are presented, while keeping both the required size of the commutation inductor, and the thyristor turn-off losses low. Efficiency estimates indicate that this concept could result in converter topologies with power losses as low as 0.3% rated power while retaining high quality current waveforms and achieving tolerance to both ac and dc faults.