Michael Putrino

Comparison of single- and dual-pass multiply-add fused floating-point units

Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low power computing market. The floating point unit occupies a significant percentage of the silicon area in a microprocessor due its wide data bandwidth (for double precision computations) and the area occupied by the multiply array. For microprocessors designed for portable products, the design site of the floating point unit plays an important role in the low cost factor driven by reduced chip area. Some microprocessors have multiply-add fused floating point units with a reduced multiply array, requiring two passes through the array for operations involving double precision multiplies. The paper discusses the design complexities around the dual pass multiply array and its effect on area and performance. Floating point unit areas and their associated multiply array areas are compared for a single and dual pass implementation in a given technology (PowerPC 604eTM and PowerPC 603eTM microprocessors, respectively).

Brief communication Condition code predictor for fixed-point arithmetic units

Abstract This paper presents a method for determining the ‘results equals zero’ condition code and, by extension, all other related condition codes for arithmetic operations. The ‘result equals zero’ condition is predicted for all arithmetic operations computed by a typical hardwired adder, and can be implemented in hardware in parallel with such an adder without implicit or explicit use of the carries.

Resolution of branching with prediction

Abstract A scheme for the resolution of branch instruction outcome is described. The branch instructions considered perform an increment operation whose result is saved, and then a comparison is made between the increment result and a comparison operand. The result of the comparison reflects the outcome of the branch. The resolution of the branch outcome is made by prediction directly from the three operands presented by the instruction. No increment or comparison need be performed explicitly to determine the branch outcome. The outcome of the branching is determined in the same amount of time as it takes to perform the increment, which in essence, is performed with a two-to-one adder, and is required as a data result of the branch instructions.

A new PowerPC microprocessor for low power computing systems

A new PowerPC microprocessor is designed for desktop companions and high end embedded multimedia applications such as high performance video games with graphics intensive operations. It features a low power consumption of 1.2 watts at 66 MHz at 3.3 volts. The processor is fabricated in a 0.5 micron, 4 level metal CMOS technology resulting in 1 M transistors in a 7.07 mm by 7.07 mm chip size. Dual 4K-byte instruction and data caches coupled to a high performance 64-bit multiplexed bus and separate execution units (branch, float, integer, and load-store units) result in a peak instruction rate of 2 instructions per clock cycle. Low power techniques are used throughout the entire design including dynamically powered down execution units.

Invited paper Parallel binary byte adder/subtracter

Recursive boolean equations are presented that can be used for hardware implementations of adders that include binary byte addition and subtraction. Normally adders of this type are used by microcode and sometimes are required by architected instruction sets. The new proposed sum equations do not depend on the carries or equivalent quantities. The advantages associated with adders designed with the new carries that are not equivalent or equal to the traditional carries, have been retained.

Parallel encrypted array multipliers

An algorithm for direct twos-complement and sign-magnitude parallel multiplication is described. The partial product matrix representing the multiplication is converted to an equivalent matrix by encryption. Its reduction, producing the final result, needs no specialized adders and can be added with any parallel array addition technique. It contains no negative terms and no extra correction rows; in addition, it produces the multiplication with fewer than the minimal number of rows required for a direct multiplication process.

Unified multi-bit overlapped-scanning multiplier algorithm

The authors introduce a unique formulation of multiplication for different notations with the unification of the multi-bit overlapped-scanning technique. Specifically, an algorithm for integer and fractional number representations is described for the twos-complement, sign-magnitude, ones-complement, and unsigned notations. It is indicated that a fractional, twos-complement multiplier with minor modifications can accommodate all the notations for integer and fractional representations. The minor modifications include the design of an (n+1)*(n+1) instead of an n*n multiplier with circuits for pre- and post-ones-complementation, and proper computation of the sign.<<ETX>>

Parity predict for 34 bit adders with selection

The authors consider 34 bit adder parity prediction schemes where the parity is predicted for either the 32 most significant or 32 least significant bits of the final 34 bit adder result, depending on the instruction being executed. Two parity prediction schemes are derived: one that considers the carries into the bytes and one that considers the carries into the nibbles. The two schemes save hardware and logic delay by grouping the adder bits common to both choices, rather than explicitly calculating the parity for the two separate 32 bit results and then choosing between them depending on the instruction performed. The hardware and its associated delay required to implement both parity predictors are of the same order of magnitude as for conventional 32 bit adder parity predictors.<<ETX>>

Direct Computation of the Polynomial Expression Ax/sup 2/ + Bx + C

The present study focuses on the realization of the polynomial expression Ax/sup 2/ + Bx + C. The computation of the polynomial expression is achieved in a parallel and pipelined structure with time and hardware savings if compared to a direct realization of the expression with explicit calculations. The layout of the hardware is simple, given the uniformity of matrices, thus suitable for VLSI design.