Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Soummya Mallick is active.

Publication


Featured researches published by Soummya Mallick.


Proceedings of COMPCON '94 | 1994

The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

Brad Burgess; Mike Alexander; Ying-wai Ho; Suzanne Plummer Litch; Soummya Mallick; Deene Ogden; Sung-Ho Park; Jeff Slaton

The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family. The 603 is a superscalar implementation featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz. The 7.4 mm by 11.5 mm design is implemented in 0.5 /spl mu/m, four-level metal CMOS technology. The 603 features dual 8-kByte instruction and data caches and a 32/64-bit system bus. Peak instruction rates of 3 instructions per clock cycle give outstanding performance to notebook and portable applications.<<ETX>>


ieee computer society international conference | 1995

A new PowerPC microprocessor for low power computing systems

Deene Ogden; Belli Kuttanna; Albert J. Loper; Soummya Mallick; Michael Putrino

A new PowerPC microprocessor is designed for desktop companions and high end embedded multimedia applications such as high performance video games with graphics intensive operations. It features a low power consumption of 1.2 watts at 66 MHz at 3.3 volts. The processor is fabricated in a 0.5 micron, 4 level metal CMOS technology resulting in 1 M transistors in a 7.07 mm by 7.07 mm chip size. Dual 4K-byte instruction and data caches coupled to a high performance 64-bit multiplexed bus and separate execution units (branch, float, integer, and load-store units) result in a peak instruction rate of 2 instructions per clock cycle. Low power techniques are used throughout the entire design including dynamically powered down execution units.


Archive | 1996

Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order

James Allan Kahle; Soummya Mallick; Robert G. Mcdonald


Archive | 1995

Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization

James Allan Kahle; Albert J. Loper; Soummya Mallick; Aubrey Deene Ogden; John Victor Sell


Archive | 1996

Method and system for executing a program within a multiscalar processor by processing linked thread descriptors

James Allan Kahle; Soummya Mallick; Robert G. Mcdonald; Edward L. Swarthout


Archive | 1996

Method and system for constructing a program including a navigation instruction

Soummya Mallick; Robert G. Mcdonald; Edward L. Swarthout


Archive | 1996

System and method for reducing power consumption in an electronic circuit

Albert J. Loper; Soummya Mallick


Archive | 1996

Latency-based scheduling of instructions in a superscalar processor

James Allan Kahle; Soummya Mallick; Robert G. Mcdonald


Archive | 1996

Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution

Soummya Mallick; Robert G. Mcdonald; Edward L. Swarthout


Archive | 1996

Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache

Rajesh Bhikhubhai Patel; Soummya Mallick

Researchain Logo
Decentralizing Knowledge