Michael R. Lightner

A Study of Variance Reduction Techniques for Estimating Circuit Yields

The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.

Simultaneous design in both magnitude and group-delay of IIR and FIR filters based on multiple criterion optimization

This work considers the simultaneous design in both magnitude and group-delay of digital transfer functions on the basis of multiple criterion optimization. Both causal IIR filters and nonlinear phase FIR filters are studied. Examples of the optimal tradeoff filters, both FIR filters and IIR filters, are presented and their characteristics are analyzed.

An Extrapolated Yield Approximation Technique for Use in Yield Maximization

This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based upon a quadratic model of the circuit. Statistical yield estimates are computed from the model and correlated sampling is used to extrapolate along the search direction. Two simple methods for determining search directions are discussed and these are used to demonstrate the overall method through several examples.

Application of the optimization program AOP to the design of memory circuits

The memory cycle time of an IGFET read-only memory cell is designed using AOP, a program for automated and interactive optimization of electrical networks. It is shown how AOP allows the user to specify multiple performance objectives and to request analysis, and/or adjoint sensitivity computation, and/or automated optimization for networks described in the ASTAP input language. A. procedure is given for applying optimization to switching circuit design, and a summary is given of the hard experience gained from applying AOP to a practical problem in LSI design.

Experiments in logic optimization

A number of experiments have been conducted to answer several important questions about logic optimization and its application to high-level synthesis. The experiments are summarised and show that: logic optimization is competitive with manual design; stronger optimization methods give somewhat better average results (10%-30%) at much greater computational cost (8* and more); fast logic optimization methods can be used to estimate the average results of the more powerful, costly methods; and literal count is a good estimator of area before routing for standard cell designs.<<ETX>>

Multiple criterion optimization with yield maximization

A number of recent papers have described circuit optimization methods in which maximizing yield was the sole design criterion. However, in actual practice there are many competing design criteria such as minimizing power and area, maximizing speed, etc., as well as maximizing yield. In this paper the techniques of Multiple Criterion Optimization (MCO) are used to provide a framework within which to consider all of these objectives simultaneously. Towards this end a theoretical foundation for the analysis of geometrically based yield algorithms is introduced. This framework can be used to investigate the yield estimation algorithms of Director, Hachtel and Brayton, and Bandler and Abdel-Malek. By combining features from both of these methods, a new yield estimation scheme is developed which is better suited to the needs of the MCO problem. The ideas of MCO and the new yield estimation procedure are applied to the design of a two-input MOSFET NAND gate.

Virtual circuit laboratory

We present the rationale, implementation and performance features of a virtual lab environment for an electronic circuits course. The primary purpose of the tool is to provide an environment that mimics some of the failure modes of a real lab, which aids the student in learning debugging techniques. The tool is implemented as a Java application.

BOLD: The Boulder Optimal Logic Design system

The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples.<<ETX>>

A modular architecture for dynamic programming and maximum likelihood sequence estimation

The communication problems of phase tracking [1-3], convolutional decoding [4,5], and dynamic time warping [6], can all be solved with a Dynamic Programming algorithm to find the shortest path through a graph. We present a modular systolic architecture for the specific problem of forming the maximum a posteriori (MAP) estimate of the sequence of visited states of an M-state Markov chain, using noisy observations of a memoryless function of the chain. The architecture is composed of three main sections: (1) a Metric Processor which pre-processes each input datum into M input metrics, (2) a Likelihood Processor which uses the input metrics and the apriori Markov model to update the likelihood measures of the M implicit survivor paths, and (3) a Path Processor which stores the array of back-pointers used to explicitly construct the single most likely survivor path. The likelihood processor is composed of a systolic ring of M simple processing elements which perform the O(M2) computations for each input in O(M) time. If the length N of the sequence is long, the pipe-lined path processor can implement sub-optimal periodic path truncation decoding, which includes the familiar fixed-lag and fixed-interval decoding.

Modeling and simulation of VLSI digital systems

Discrete simulation of digital circuits is a vital tool in the design process. However, few people are aware of the modeling assumptions inherent in discrete simulation. Nor is there a widely accepted and consistent theory of modeling and simulation of discrete/digital systems. In this paper we concentrate on the basic ideas behind discrete modeling and present a discussion of the most popular algorithms used in writing simulators. In addition, we use the characteristics of discrete models to define the logic, functional, and behavioral levels of simulation. In closing, we discuss new issues in modeling and simulation.