Michael R. Scheuermann

Physical design of a fourth-generation POWER GHz microprocessor

The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.

Magnetron sputtering and laser patterning of high transition temperature Cu oxide films

High Tc Y‐Ba‐Cu‐O films have been prepared by dc magnetron sputtering of metal alloy targets. To circumvent the negative ion effect, two alloy targets, YCu and BaCu, are sputtered in an argon atmosphere with an oxygen spray near the substrate. Films deposited on sapphire with onsets at 92 K and a 6° transition width (10–90%) have been achieved using this technique. These films have been successfully patterned with the technique of laser ablation.

Micropatterning of high Tc films with an excimer laser

Micron‐wide lines of high Tc Y‐Ba‐Cu‐O have been successfully patterned by ablating the films with a pulsed excimer laser. The high Tc films are mounted onto a computer‐controlled stepping stage and irradiated with a demagnified image of a variable‐size rectangular aperture. This technique has been used for fabricating features ranging from several centimeters in length to submicron in width without any degradation in Tc. For example, a superconducting microstructure of Y‐Ba‐Cu‐O, nominally 1 μm wide and 2.5 μm long, with a Tc (R=0) of 88 K and a Jc of 5×104 A/cm2 at 4.2 K was fabricated.

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential application of 3DI [2]. This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM [3] and logic blocks from the IBM Power7™ processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology [4] enhanced to include through-silicon vias (TSVs) [5]. Unlike the previously reported 3D eDRAM [6], the 3D stack described here is constructed using 50μm pitch μC4s joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ~20μm in diameter and <;100μm deep [5].

Time-of-flight measurements of minority-carrier transport in p-silicon

The electric field dependence of electron mobilities in p‐type silicon with doping density of 4.5×1016 cm−3 at room temperature was measured using a time‐of‐flight technique. It was found that the electron mobility at zero field is very close to that in n‐type silicon of equivalent doping density; however, it decreases rapidly with electric field in a range from 0 to 0.2 kV/cm and more gradually at higher fields. The effect is attributed to the electron‐hole scattering.

Modeling of power delivery into 3D chips on silicon interposer

While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (Vdd)variation over time for 3D systems in a manner of maximum accuracy and efficiency.

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

In this paper, we present a transient modeling of electromigration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs. In particular, we model atomic depletion and accumulation, effective resistance degradation, and full chip-scale PDN lifetime degradation due to EM. Our major focuses are on: (1) time-dependent multi-physics EM modeling approach to model TSVs and connecting wires under the influence of coupled physical phenomenon including electric field, temperature, and stress; (2) time-dependent EM-aware power integrity analysis methodology, which is integrated with the TSV modeling approach to predict long-term IR-drop degradation in full-chip 3D power delivery networks. Our studies show that voids and hillocks grow at various TSV-to-wire interfaces and degrade the effective resistance of TSVs significantly. In addition, our full-chip PDN lifetime analysis shows significant increase in maximum IR drop during lifetime due to EM effects.

Seebeck and Nernst effect in the mixed state of slightly oxygen deficient YBaCuO

Abstract For an epitaxial c -axis oriented slightly oxygen deficient YBaCuO film, showing a positive Seebeck coefficient around 100 K, the Nernst effect has been measured in the mixed state for magnetic fields up to 9 T. The transport entropy calculated in the usual way is about an order of magnitude smaller than for a similar but fully oxygenated film with a negative Seebeck coefficient near 100 K. This can be explained by the enhanced decoupling of the CuO 2 planes in the slightly oxygen deficient material, resulting in a strong departure of the vortices (“pancake vortices”) from the standard Abrikosov type.

DC Sqiids made from YBa2Cu3Oy

Abstract This paper reports on progress made at IBM in the fabrication of HiTc dc SQUIDs (Superconducting QUantum Interference Devices) 1,2 . We have fabricated SQUIDs from polycrystalline YBa 2 Cu 3 O y samples on MgO substrates 3 and from epitaxial films on SrTiO 3 (100) substrates 4 . The films were patterned using either ion-implanting to selectively convert the superconductor into an insulator without actually removing any material 1,5 , laser ablation to pattern a loop into the film by removing material 6 , or a conventional ion milling process to selectively remove material using a photoresist mask. In the case of the polycrystalline films, the naturally occurring grain boundaries provide the weak link or Josephson junction behavior in a stripe that is much larger in size than the superconducting coherence length. We have measured the noise amplitude of one such SQUID made on MgO to be about1 × 10 -5 Φ O /Hz 1/2 at 1000 Hz and 40 K. Loops formed from true epitaxial films containing many twin boudaries will not operate as dc SQUIDs unless the films are damaged across each link. A SQUID formed in this way operated in liquid nitrogen and had an estimated white noise performance of1 × 10 -3 Φ 0 /Hz 1/2 at 74 K.

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis.