Michael S. Obrecht

Low-power direct digital frequency synthesis for wireless communications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

Impact of technology scaling on CMOS RF devices and circuits

In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 /spl mu/m, 0.25 /spl mu/m, 0.35 /spl mu/m, 0.5 /spl mu/m and 0.8 /spl mu/m. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 /spl mu/m for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 /spl mu/m and 50 /spl mu/m for the 0.8 /spl mu/m and 0.18 /spl mu/m gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 /spl mu/m and 0.18 /spl mu/m CMOS processes, respectively. This reduction in current is due to the fact that g/sub m//I/sub ds/ for a 0.18 /spl mu/m process is 25 V/sup -1/ whereas it is equal to 5 V/sup -1/ for a 0.5 /spl mu/m process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver.

Diffusion current and its effect on noise in submicron MOSFETs

Reports a significant shot noise component in submicron metal-oxide-semiconductor field effect transistors (MOSFETs) operating in strong inversion. A quasi-three-dimensional (3D) MOSFET simulation was used to compare simulated noise parameters to measured data and to verify the model. For long channel devices, thermal noise was confirmed to be the main source of noise in accord with the conventional theory. In contrast, for submicron devices the shot noise appeared to be dominant. The shot noise component is primarily produced near the source of the device and is believed to be caused by the diffusion current.

A low-power direct digital frequency synthesizer architecture for wireless communications

A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 /spl mu/m CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation.

RF simulations and physics of the channel noise parameters within MOS transistors

In this paper we report results for the RF channel noise parameters of MOS transistors. Our hope is that these results will provide RF CMOS circuit designers with a better understanding of the noise properties of a MOS device. The results were obtained from a physically based 2-D device noise simulator. The simulator inherently takes into account the microwave noise sources within the transistor. The drain channel noise as well as the induced gate noise are presented. The results show that drain channel noise is strongly influenced by short channel effects whereas induced gate noise is not. Furthermore, the excess noise in the channel due to hot electrons near the drain was determined to be less important than normally thought.

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported. >

TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices

A new software tool TRASIM (Two-Dimensional Transient Simulator) has been developed for arbitrary, planar semiconductor devices. A finite difference technique is employed with a modified, decoupled Gummel-like method. The memory requirements are reduced significantly compared to the conventionally used Newton-like methods. TRASIM exhibits a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and efficiency make the method attractive for the future 3-D applications. The software uses the drift-diffusion model, with up-to-date mobility and lifetime models. External RC-chains may be connected to device electrodes. Numerical examples are presented illustrating the advantages of the modified Gummel method over the Newton method, for transient simulation. >

RF noise characterization of MOS devices for LNA design using a physical-based quasi-3-D approach

A quasi-3-D method for microwave noise simulation of MOSFET is presented in this paper. This method inherently takes into account all the microscopic noise sources within the transistor at microwave frequencies. It is realized by properly transforming the 2-D noise sources to 3-D equivalent noise sources. The 2-D noise sources and their correlation term are calculated in the framework of a PDE based 2-D device simulator. Based on 3-D equivalent noise network, the four noise parameters F/sub min/, R/sub n/, R/sub opt/, and X/sub opt/ which are critical for low noise device design are calculated. A 0.5 -/spl mu/m LDD nMOS transistor was simulated and the simulation results were compared to measurement data. The functional behavior of the four noise parameters at microwave frequency with bias and layout parameters is illustrated. An example for designing a low noise MOSFET for RF application is provided.

High-frequency dependence of channel noise in short-channel RF MOSFETs

Using a two-dimensional (2-D) Greens function technique, similar to Shockleys impedance field technique, simulation results of the drain i/sub d/ and gate induced i/sub g/ channel noise are presented for an nMOS transistor as a function of frequency. The simulation results show that for frequencies much lower than the cutoff frequency of the transistor f/sub t/ the correlation factor (i.e., i~/sub g~/i~*/sub d~///spl radic/i/sub g//sup -2/i/sub g//sup -2/) between the drain and gate channel noise is equal to approximately 0.4j. For frequencies near the f/sub t/ of the device the correlation factor approximately equals 0.3j. For f/f/sub t//spl sim/0.3, the contribution of the gate induced noise compared to the drain noise was found to be on the order of 1% (i.e., i/sub g//sup -2//i/sub d//sup -2/(f/sub t//f)/sup 2/).

Simulation of Temperature Dependence of Microwave Noise in Metal-Oxide-Semiconductor Field-Effect Transistors

We present results of a two-demensional (2D) numerical simulation of high-frequency noise in a short-channel metal-oxide-semiconductor field-effect transistors (MOSFET). Conventionally this noise in MOSFETs is treated as a thermal noise with a rather slow temperature dependence of the noise spectra. On contrary, the results obtained indicate that this dependence is more of an exponential kind, typical for a shot noise. Shot noise is conventionally related to a forward biased p-n junction where the current is mostly due to diffusion in the quasi-neutral region. We therefore speculate that most likely in short channel MOSFETs most of the high-frequency noise is produced not in the cut-off region of the channel but near the source side of the channel where diffusion current component is dominant.