Michael Scheppler

Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone

Circuit arrangement for supplying configuration data in FPGA devices

Look-up table

Logic circuit arrangement

Configurable logic component without a local configuration memory and with a parallel configuration bus

Mask-programmable logic macro and method for programming a logic macro

Logik-Schaltkreis-Anordnung

Mask-programmable logic macro

Special semiconductor circuit and resource configuration method for semiconductor circuit driver

Maskenprogrammierbares Logikmakro Mask Programmable logic macro