Siegmar Koeppe

A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on state-of-the-art TDCs is given. A high-resolution TDC with low latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally interpolated with passive voltage dividers. This high-resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved. The resolution restrictions imposed by an uncertainty of the stop signal and local variations are derived theoretically.

90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization

Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High-resolution TDCs become increasingly popular for time-of-flight measurements, full-speed testing, e.g., jitter measurement, clock and data recovery, measurement and instrumentation, and digital PLLs. As the speed leverage of technology scaling decreases below 100nm, robust TDCs with sub-gate-delay resolution are essential. The Vernier TDC requires long delay lines, thus suffers from large latency, area and power consumption. Latency and a resolution limited by the inherent variation-related pulse-width modification are the drawbacks of the pulse-shrinking approach. Parallel gradual-delay elements are particularly susceptible to process variations. The same holds for analog operations on time intervals like delay amplification. Ultra high-resolution TDCs achieve sub-ps resolution but require iterative conversion.

Design and Application of Power Optimized High-Speed CMOS Frequency Dividers

Frequencies in the gigahertz range translate switching activity and internal node capacitance quickly to high power values. Therefore, the power optimized design of high-speed CMOS logic-based frequency dividers is sensitive to circuit partitioning and selection of flip-flop-type and logic family. On the basis of two circuit examples, the design of highly power optimized dividers based on conventional CMOS logic is demonstrated. First, a divide-by-15 circuit based on sense-amplifier and master-slave flip-flops is discussed. A 5.5-GHz demonstrator implemented in a 90-nm low-power CMOS technology consumes only 190 muW/GHz for a supply voltage of 1.1 V. Second, an even faster CMOS divider concept without static power consumption, except leakage power, is proposed. The circuit divides an input signal by two and generates four phases with highly accurate phase skew of 90 deg. The maximum operation frequency is 11.6 GHz for a supply voltage of 1.5 V, slow process and worst case operation parameters. Higher frequencies can be achieved by a hybrid approach where the signal is first divided by a factor of two in a single current mode logic (CML) stage and then by the proposed circuit by another factor of two for the generation of the four phases. The divider is applied to dual modulus pre-scalers and IQ receivers. A variant of the circuit contains an intrinsic phase-rotator, allowing pre-scalers without any phase synchronization. Therewith, the power consumption is not only reduced due to the efficient divider implementation but also by a simplified architecture of the overall pre-scaler.

High-speed low-power frequency divider with intrinsic phase rotator

A CMOS divider concept without static power consumption, except leakage power, is proposed. The circuit divides an input signal by two and generates four phases with highly accurate phase skew of 90 degrees. In a 90nm low-power CMOS technology, the maximum operation frequency is 11.6 GHz for a supply voltage of 1.5V slow process and worst case operation parameters. Higher frequencies can be achieved by a hybrid approach where the signal is first divided by a factor of two in a single CML stage and then by the proposed circuit by another factor of two for the generation of the four phases. The divider is applied to dual modulus pre-scalers and IQ receivers. A variant of the circuit contains an intrinsic phase-rotator, so the power consumption of the pre-scaler is not only reduced due to the logic style but also by a simplified architecture of the overall pre-scaler