Michael Thomas Brady

Vector processing in scalar processors for signal processing algorithms

Product requirements often dictate the use of off-the-shelf processors for very fast signal processing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required.

High-speed multilevel halftoning hardware

A high speed multilevel color printer required custom halftoning hardware. For this multitone environment we revised traditional halftone thresholding (i.e. turning the output from no intensity to full intensity). Unfortunately, intermediate values did not print large areas reliably. Legacy image data files existed that were already halftoned. To correct these problems, binary halftone methods were modified to produce multi-bit outputs. This was accomplished by using threshold matrices to determine when to allow printing. The input minus the threshhold value was used to index into a lookup table to select the output intensity. Design of the down-loadable threshold matrices solved the print consistency problem. The custom hardware ensured that a zero input value did not print and a maximum value printed as a saturated output. These solutions were implemented using custom high-speed logic capable of outputting 66 MegaPels/sec.