Michael W. Beattie

Inductance 101: modeling and extraction

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This tutorial paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as the skin and proximity effect.

Efficient inductance extraction via windowing

We propose a new, efficient and accurate localized inductance modeling technique via windowing in a manner that is analogous to localized capacitance extraction. The stability and accuracy of this process is made possible by twice inverting the localized inductance models, and in the process exploiting properties of the magnetostatic interactions as modeled via the susceptance (inverse inductance). Application of these localized double-inverse inductance models to actual IC bus examples demonstrates the significant improvement in simulation efficiency and overall accuracy as compared to alternative methods of approximation and simplification.

Modeling magnetic coupling for on-chip interconnect

As advances in IC technologies and operating frequencies make the modeling of on-chip magnetic interactions a necessity, it is apparent that extension of traditional inductance extraction approaches to full-chip scale problems is impractical. There are primarily two obstacles to performing inductance extraction with the same efficacy as full-chip capacitance extraction: (1) neglecting far-away coupling terms can generate an unstable inductance matrix approximation; and (2) the penetrating nature of inductance makes localized extraction via windowing extremely difficult. In this paper we propose and contrast three new options for stable and accurate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to consider the possibilities for pattern-matching style solutions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.

IC analyses including extracted inductance models

IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of these results with the IC interconnect resistance and capacitance models significantly complicates most IC design and verification methodologies. In this tutorial paper we will review some of the analysis and verification problems associated with on-chip inductance, and present a subset of recent results for partially addressing the challenges which lie ahead.

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement

The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings beyond the localized confines of functional design blocks. In addition, SOC design styles and gridless variable-width routing make it increasingly difficult to use precharacterized library shapes for parasitic extraction. A comprehensive capacitance and inductance extraction solution requires a hierarchical data representation and fast runtime algorithms. We illustrate through examples that both the multipole method and hierarchical refinement, which are the two most successful approaches for parasitic extraction to date, work efficiently only under certain, limiting conditions. To improve this situation we present an approach which combines the best of both methods into a concurrent multipole refinement representation of the electromagnetic interaction which is efficient for arbitrary interconnect configurations. We use a generalized formulation of electromagnetic interactions to exploit the similarities in capacitance and inductance extraction for greater efficiency.

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses

Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of the magnetic couplings for final design verification can be a daunting task. In general, when modeling inductance and the associated return paths, one must consider the on-chip conductors as well as the system packaging. This can result in an RLC circuit size that is impractical for traditional simulators. In this paper we demonstrate a localized, window-based extraction and simulation methodology that employs the recently proposed susceptance (the inverse of inductance matrix) concept. We provide a qualitative explanation for the efficacy of this approach, and demonstrate how it facilitates pre-manufacturing simulations that would otherwise be intractable. A critical aspect of this simulation efficiency is owed to a susceptance-based circuit formation that we prove to be symmetric positive definite. This property, along with the sparsity of the susceptance matrix, enables the use of some advanced sparse matrix solvers. lye demonstrate this extraction and simulation methodology on some industrial examples.

Equipotential shells for efficient inductance extraction

To make three-dimensional (3-D) on-chip interconnect inductance extraction tractable, it is necessary to ignore parasitic couplings without compromising critical properties of the interconnect system. It is demonstrated that simply discarding faraway mutual inductance couplings can lead to an unstable approximate inductance matrix. In this paper, we describe an equipotential shell methodology, which generates a partial inductance matrix that is sparse yet stable and symmetric. We prove the positive definiteness of the resulting approximate inductance matrix when the equipotential shells are properly defined. Importantly, the equipotential shell approach also provably preserves the inductance of loops if they are enclosed entirely within the shells of their segments. Methods for sizing the shells to control the accuracy are presented. To demonstrate the overall efficacy for on-chip extraction, ellipsoid shells, which are a special case of the general equipotential shell approach, are presented and demonstrated for both on-chip and system-level extraction examples.

On-chip induction modeling: basics and advanced methods

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as skin and proximity effect. We also discuss and contrast options for stable and accurate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to consider the possibilities for pattern-matching style solutions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.

Parallelized Full Package Signal Integrity Analysis Using Spatially Distributed 3D Circuit Models

Full package signal integrity analysis is parallelized in a suite of tools called PATS (package analysis tool suite). PATS extracts sparse circuit models using a segment-to-segment BEM (boundary element method) algorithm for both capacitance and inverse inductance and uses a fixed-time step circuit simulator to create time-domain scattering models. Critical issues regarding the parallelization of PATS and segment-to-segment BEM circuit models are explored. Examples demonstrating the accuracy of this approach are presented for real packaging cases

Equipotential shells for efficient partial inductance extraction

The shift-truncate potential method was introduced as an approach to sparsify the partial inductance matrix while maintaining the stability and symmetry. This was accomplished with the use of spherical return shells around point-like current segments. In this paper we propose the use of filament current distributions for the same purpose. Ellipsoidal shells are introduced to model the equipotential surfaces for filament currents. Importantly, we prove that the positive definiteness of the resulting sparse partial inductance matrix is preserved for this and all other potential-shell models when the compensating currents are placed on equipotential surfaces of the original current distribution. The utility and efficiency of this ellipsoidal shell partial inductance approximation are demonstrated for both on-chip and system-level extraction examples.