Michael W. Parkin

The S3.mp scalable shared memory multiprocessor

S3.mp (Suns Scalable Shared memory MultiProcessor) is a research project to demonstrate a low overhead, high throughput communication system that is based on cache coherent distributed shared memory (DSM). S3.mp uses distributed directories and point-to-point messages that are sent over a packet switched interconnect fabric to achieve scalability over a wide range of configurations. S3.mp uses a new CMOS serial link technology that achieves transmission rates >1 Gbit/sec and that is directly integrated into a packet router chip. Unlike other DSM systems, S3.mp can be spatially distributed over a local area via fiber optic links. This capability allows S3.mp to interconnect clusters of workstations to form multiprocessor workgroups that efficiently share memory, processors and I/O devices. Multichip module technology, the integrated arbitrary topology router, fast serial links, and a DSM system that is integrated into the memory controller allow compact, massively parallel S3.mp systems.<<ETX>>

S-connect: from networks of workstations to supercomputer performance

S-Connect is a new high speed, scalable interconnect system that has been developed to support networks of workstations to efficiently share computing resources. It uses off-the-shelf CMOS technology to directly drive fiber-optic systems at speeds greater than 1 Gbit/sec and can realize bisection bandwidths comparable to high-end MPP systems while being >10x more cost-effective. S-Connect systems do not rely on centralized switches, but rather are composed of adaptive, topology independent routing elements that are integrated into each node. The S-Connect routing algorithm is optimized for fine grained, irregular traffic and is designed to support high traffic loads, that can utilize most of the physically available bandwidth. Such traffic is typical of a distributed shared memory system, which is one of the intended applications. S-Connect innovations include a novel distributed phase locking method that allows global synchronization, HW support for multiple message priorities, in-band monitoring and control facilities, and a low overhead channel protocol that supports multiple in-transit messages on the same fiber. The first version of the S-Connect switching element has been successfully, implemented in a commercial 0.65 /spl mu/m CMOS process.

Exploiting Parallelism in Cache Coherency Protocol Engines

Shared memory multiprocessors are based on memory models, which are precise contracts between hard- and software that spell out the semantics of memory operations. Scalable systems implementing such memory models rely on cache coherency protocols that use dedicated hardware. This paper discusses the design space for high performance cache coherency controllers and describes the architecture of the programmable protocol engines that were developed for the S3.mp shared memory multiprocessor. S3.mp uses two independent protocol engines, each of which can maintain multiple, concurrent contexts so that maintaining memory consistency does not limit the system performance. Programmability of these engines allows support of multiple memory organizations, including CC-NUMA and S-COMA.

The S3.mp architecture: a local area multiprocessor

The S3.mp prototype system is being irnplentented by SMCC’S Technology Development group to demonstrate a low overhead. high throughput communication systan tltat is based on distributed shared memory (DSM). Conceptually, S3.mp is a virtual busextertder that preserves the semantics of accesing memory across alt nodes. Unlike multiprocessor busses that use broadcast

Method and apparatus for simulation system compiler

tg to preserve memory coherency, S3.mp uses directories and #xrqt-topoint messages over a packet switched interconnect abrlc to achieve scalabfity over a tie range of system cordigurations. communication technology advances, such as high speed fiber optics, are the driving force behind the S3.mp develcpmen~ While it is technically easier to utilize the increasa.d bandwidth with conventional DMA devi=, the resulting message passing hardware re@res substantial software overhead to process protocol stacks, manage bufkxs, encode apd decode messag=y etc. In S3.mp, communication happens as a st&-effect of accemng memory a single store or load instruction is sufficient to send or receive data. The set of transactions that are required to support the DSM paradigm is small and well delined w that the S3.mp protocols were amenable to formal verification methods and are implemented directly in hardware. S3.mp systems are similar to ALEWILE, DASH, PLUS and other nonuniform memory access multiprocessors. However untike th= conventional NUMA MPs, wtuch strive to det.iwx the most IvfFtops to one.scientdic application, S3.mp is optimized for a large collection of independent applications that share common comptttin resources which maybe spatially distributed. Conse

The S3.mp Scalable Shared Memory Multiprocessor.

qtrently, 3.mp nodes maybe separated by up to 200m, which mean that a S3 .m s stem could be distributed over an entire tial{ building. Essen y, 3.mp systemsare build by adding a specialLzJirti:hcoutect controller to the memory subsystem of a norrnat