Michael Zervas

Photonic Damascene process for integrated high-Q microresonator based nonlinear photonics

High confinement, integrated silicon nitride (SiN) waveguides have recently emerged as an attractive platform for on-chip nonlinear optical devices. The fabrication of high-Q SiN microresonators with anomalous group velocity dispersion has enabled broadband nonlinear optical frequency comb generation. Such frequency combs have been successfully applied in coherent communication and ultrashort pulse generation. However, the reliable fabrication of high confinement waveguides from stoichiometric, high stress SiN remains challenging. Here we present a novel photonic Damascene fabrication process enabling the use of substrate topography for stress control and thin film crack prevention. With close to unity sample yield we fabricate microresonators with 1.35 mu m thick waveguides and optical Q-factors of 3.7 x 10(6) and demonstrate single temporal dissipative Kerr soliton based coherent optical frequency comb generation. Our newly developed process is also interesting for other material platforms, photonic integration, and mid-infrared Kerr comb generation

Applications of Multi-Terminal Memristive Devices: A Review

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show examples of two-terminal Resistive RAMs (ReRAM) for standalone memory and Field Programmable Gate Arrays (FPGA) applications. Moreover, a Generic Memory Structure (GMS) utilizing two ReRAMs for 3D-FPGA is discussed. In addition, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/semiconductor surface. The combination of these two memristive effects into multi-terminal MOSFET devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. Finally, the multi-terminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid CMOS co-fabrication with a CMOS-compatible process.I.

Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics

In this letter, we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) cointegration with 380 μm-height Cu through-silicon via (TSV) arrays for programmable 3-D interconnects. Nonvolatile resistive switching of Pt/TiO2 /Pt thin films is first characterized with a resistance ratio up to five orders of magnitude. Then, cointegration of Pt/TiO2/Pt or Pt/TiO2 memory cells on 140 and 60 μm diameter Cu TSVs is fabricated. Repeatable nonvolatile bipolar switching of the ReRAM cells is demonstrated for different structures.

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3-D network-on-chip (NoC), which can route packets in the vertical direction. Superimposing identical planar dies minimizes design effort and manufacturing costs, ensuring at the same time high flexibility and reconfigurability. A single die can be used either as a fully testable standalone chip multi-processor (CMP), or integrated in a 3-D stack, increasing the overall core count and consequently the system performance. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90 nm complementary metal-oxide-semiconductor process and stacked using an in-house, via-last Cu-TSV process. Initial results show that the proposed 3-D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gb/s.

Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Three-dimensional (3D) stacking of integrated-circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single- and two-phase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.

Fabrication and characterization of wafer-level deep TSV arrays

Three Dimensional (3D) integration, based on through silicon vias (TSV), has the potential to become a key enabling technology for many applications. TSVs are commonly categorized according to their aspect ratio and diameter. An equally important parameter of the TSV, usually omitted, is their depth. This paper discusses the fabrication process, characterization and detailed failure analysis of deep Cu TSVs, with high aspect ratio. For the proposed process, TSVs are etched on a 380μm thick wafer using standard deep reactive ion etching (DRIE). The electroplating is performed in two steps, the first step seals off one side of the TSV using super conformal chemistry, Dow chemical Intervia™ 8520 bath, and the second step uses the now partially filled via as a seed layer for a bottom up technique, bath Intervia™ 8510 or Intervia™ 8520 Dow Chemical. After the electroplating, a chemical-mechanical polishing (CMP) step is used to planarize the wafer, and double-sided metal sputtering and photolithography are performed to connect the TSVs in a daisy chain. A conventional bonding technique, like solder bumps, can be used to bond layers with TSVs.

Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon

An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

A CMOS-compatible chip-to-chip 3D integration platform

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-level. A parylene deposition technique developed throughout this research provides a very flat wafer surface after chip embedding, thus, photoresist spin-coating and patterning can easily be performed in wafer-level. For a full-wafer exposure by a mask aligner, 5μm mask-to-chip alignment accuracy is achieved in average. In the preliminary tests, two dummy chips are successfully bonded, and TSVs with parylene sidewall passivation and electroplated Cu metallization are fabricated. The daisy-chain resistance measurements demonstrate average TSV resistance of 0.5Ω. The proposed technique introduces a simple and low-cost solution not only for 3D integration technology but also for applications involving CMOS post-processing in general, especially when the full-wafer CMOS is not affordable or not possible to post-process due to compatibility issues.

Double inverse nanotapers for efficient light coupling to integrated photonic devices

Efficient light coupling to integrated photonic devices is of key importance to a wide variety of applications. Inverse nanotapers are widely used, in which the waveguide width is reduced to match an incident mode. Here, we demonstrate novel double inverse tapers, in which we reduce both the waveguide height and width. We demonstrate >45% chip-through coupling efficiency for both the transverse electric and transverse magnetic polarizations in Si3N4 tapers of >500u2009u2009nm width, in comparison to regular inverse tapers that necessitate <100u2009u2009nm width. The double inverse tapers show polarization-independent coupling and allow the fabrication using photolithography, relevant for applications at near-infrared and visible wavelengths, e.g.,xa0supercontinuum and soliton microcomb generation.

A chip-based silicon nitride platform for mid-infrared nonlinear photonics

We developed a chip-based silicon nitride platform with thick waveguides (> 2 μm) that overcomes the usual fabrication limitation. We demonstrate both microresonator frequency comb generation at 2.5 μm and supercontinuum generation extending beyond 4.0 μm in this platform.