Michal Cutler

Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy

Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after reconfiguration, and to increase the manufacturing yield and the operation reliability. An optimization technique for allocating the redundant cells into both levels is presented. The operational reliability and manufacturing yield of arrays with two-level redundancy are presented. The yield estimation problem is modeled by an occupancy problem in classical combinatorial analysis. Both distributed and clustered defects are taken into consideration in the yield estimation. >

The portrait of a common HTML web page

Web pages are not purely text, nor are they solely HTML. This paper surveys HTML web pages; not only on textual content, but with an emphasis on higher order visual features and supplementary technology. Using a crawler with an in-house developed rendering engine, data on a pseudo-random sample of web pages is collected. First, several basic attributes are collected to verify the collection process and confirm certain assumptions on web page text. Next, we take a look at the distribution of different types of page content (text, images, plug-in objects, and forms) in terms of rendered visual area. Those different types of content are broken down into a detailed view of the ways in which the content is used. This includes a look at the prevalence and usage of scripts and styles. We conclude that more complex page elements play a significant and underestimated role in the visually attractive, media rich, and highly interactive web pages that are currently being added to the World Wide Web.

A Microprogrammed Computer Simulator

A software educational tool (ET) has been developed that enables students of computer architecture to simulate a wide variety of computers on a fixed microprogram-organized-hardware (MOH). The user defines a computer by using ET to enter the appropriate microprogram. Machine language programs (macroprograms) may then be entered and a simulation made of their execution on the computer defined by the microprogram. While the simulated run is occurring, the state of the underlying machine may be observed at any point of execution. A microstep/graphics run mode may also be used to present a color display of the data path section of the MOH after each microinstruction is executed. In this paper, the ET simulation program, the MOH machine, and a simple example of how ET is used are presented.

Using Visual Features for Fine-Grained Genre Classification of Web Pages

The field of automatic genre classification has primarily focused on extracting textual features from documents. The goal of this research is to investigate whether visual features of HTML web pages can improve the classification of fine-grained genres. Intuitively it seems that this should be helpful and the challenge is to extract those visual features that capture the layout characteristics of the genres. A corpus of Web pages from different e-commerce sites was generated and manually classified into several genres. Three different sets of features were compared - one with just textual features, one with HTML level features added, and a third with visual features added. Our experiments confirm that using HTML features and particularly URL address features can improve classification beyond using textual features alone. We also show that adding visual features can be useful for further improving fine-grained genre classification.

Resource allocation during tests for optimally reliable software

In this research, we develop a framework for performing resource allocation (budget and time) during the test process of a software system. The framework allows the usage of different reliability models. The assumed test process includes unit, integration and system tests. The process of testing each software component (i.e., the code associated with each test) is viewed as a sequence of test and repair periods. Each test and repair period consists of a test time interval, and a repair time interval. We assume that a software system has been specified, designed and coded, and that a test plan for testing the system is available. The test plan includes a hierarchy of planned tests, and possibly constraints on the number of test and repair periods for each planned test. In addition reliability requirements may be given for some parts of the software system. The system may include a number of modules and programs.A model has been developed with the goal of finding the maximum reliability of the software system while satisfying the following constraints: total test cost cannot exceeds a given budget and requirements regarding the number of test and repair periods, and minimum reliability of components must be satisfied.The model has been solved for a variety of different constraints and parameter values using the Solver Add-in of Microsoft Excel.

Optimal software implementation considering reliability and cost

Abstract Software is becoming central to every aspect to our life. Therefore, developing highly reliable software while considering budget limitations is becoming very important. Because of their increasing complexity, software products are implemented using available modules and by performing many programming, testing and integrating tasks. The purpose of this research is to allocate resources efficiency to these activities so that the reliability of a software package will be maximized. The paper includes an optimization model for deriving cost allocations while satisfying a budget constraint. The model allows a decision maker to consider the usage of available modules in the market as well as the option of developing them in-house. It is becoming increasingly difficult to create software products that simultaneously provide high reliability, rapid delivery and low cost. This research deals with the cost of achieving reliable software. Assume a software package has been designed and is ready for implementation. To implement this software package, a set of modules will have to be purchased and many programming and integration tasks will have to be performed. The performance of a programming task consists of the detailed design of a module, coding and unit testing. An integration task consists of the additional testing and debugging needed when the code included in separately tested tasks is joined together. The implementation process ends when the package has been integrated and tested. A model for deriving cost allocations is presented. The objective of the model is to maximize reliability while satisfying a budget constraint. The option of developing modules in-house as well as the option of purchasing them if available are considered in the optimization. The paper includes a branch and bound scheme to derive an optimal solution.

Microprogrammed computer simulator tools

A versatile microassembler and assembler program is described that was developed to facilitate the preparation of symbolic microprograms and assembly language programs for use with the microprogrammable computer simulator ET (educational tool) previously reported by the authors (see ibid., vol.E-30, p.135, Aug. 1987). The microassembler program takes as input a microprogram source file written in symbolic form and produces files ready for loading into the simulators control ROM and address ROM. In addition, a file containing the mnemonics and corresponding op-codes of each instruction in the instruction set of the machine being simulated by the microprogram is created. The assembler program uses this file together with a user-written symbolic assembly language source program and produces a file containing machine language object code ready for loading into the simulators RAM. Both the microassembler and the assembler also produce list files that may be examined by the user. Students of computer architecture indicate that use of these tools, in conjunction with the ET simulator, greatly simplifies the task of learning how microprogrammed computers function. >

Self-diagnosis of failures in VLSI tree array processors

The authors present a built-in self-test and diagnosis scheme for detecting and locating the faulty cells in a tree array. Since the signatures of all cells are generated simultaneously (i.e., parallel testing), the time required for the signature generating stage is constant, independent of the array size. Each cell (processing element) generates pseudorandom test patterns and compresses test responses into a signature. By comparing signatures, the signature for the fault-free processor is found and used to locate faulty processors. For arrays with distributed faults, a tree array is partitioned into subtrees on which the diagnosis algorithm is applied in parallel. The time complexity of the diagnosis algorithm is derived. >

Categorizing Queries by Topic Directory

The categorization of a Web user query by topic or category can be used to select useful Web sources that contain the required information. In pursuit of this goal, we explore methods for mapping user queries to category hierarchies under which deep Web resources are also assumed to be classified. Our sources for these category hierarchies, or directories, are Yahoo! Directory and Wikipedia. Forwarding an unrefined query (in our case a typical fact finding query sent to a question answering system) directly to these directory resources usually returns no directories or incorrect ones. Instead, we develop techniques to generate more specific directory finding queries from an unrefined query and use these to retrieve better directories. Despite these engineered queries, our two resources often return multiple directories that include many incorrect results, i.e., directories whose categories are not related to the query, and thus Web resources for these categories are unlikely to contain the required information. We develop methods for selecting the most useful ones. We consider a directory to be useful if Web sources for any of its narrow categories are likely to contain the searched for information. We evaluate our mapping system on a set of 250 TREC questions and obtain precision and recall in the 0.8 to 1.0 range.

Distributed self-diagnosis of VLSI mesh array processors

A distributed self-diagnosis algorithm for VLSI mesh arrays with small clusters of faults is presented. It allows only fault-free cells to make decisions and to propagate diagnosis results. Its time complexity is constant with respect to the number of processors. The diagnosability is proportional to the array size.<<ETX>>