Michal Pavlik
Brno University of Technology
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Publication
Featured researches published by Michal Pavlik.
international conference on systems | 2008
Steffan Pavel; Michal Pavlik; Radimir Vrba
This paper presents design and assembly of mixed electronic circuitry for measured signal processing of the capacitive difference pressure sensor, as well as analysis of the obtained results. The smart pressure sensor provides values of measured pressure via 4-20 mA current loop output. The loop current is also used for sensor circuitry supplying. This means that current consumption of the whole sensor electronics should be less than 3.5 mA even in extended industrial temperature range from -40 to +125degC.
instrumentation and measurement technology conference | 2007
Jiri Haze; Radimir Vrba; Lukas Fujcik; J. Forejtek; P. Zavoral; Michal Pavlik; Linus Michaeli
The paper deals with bandpass sigma-delta modulator (BP SDM), which is used for conversion of signal from capacitive pressure sensor. This approach is absolutely new and unique, because this kind of modulators is utilized only for wireless and video applications. The main advantage of BP SDM is due to its defined band. That is why it is resistant against offsets of its subcuircits. Another important advantage is low power consumption, since the BP SDM digitizes only narrow band instead of whole Nyquist band with similar dynamic range. The paper shows basic ideas of this approach and simulation results with ideal and real modulator. The main stages are implemented in switched-capacitor (SC) technique. The modulator layout is presented as well.
international conference on networking | 2006
Michal Pavlik; Radimir Vrba; Pavel Steffan
This paper describes the design and construction of an electronic interface for the differential capacitance sensor of pressure. The 14-bit precision of measurement is required. The total power consumption below 5 mW and galvanic separation is needed.
international conference on telecommunications | 2016
Michal Pavlik; Vilem Kledrowetz; Marek Bohrn; Vojtech Dvorak; Lukas Fujcik
The article deals with the design of handheld potentiostat instrument utilizing an ASIC. It briefly shows complete system and control software as well. The FPGA is used to generation of the measuring potential waveform and for communication with AD and DA converters and with PC. The designed ASIC that forms the core of the instrument consists of an output buffer and a current to voltage converter with selectable measurement range. The reached parameters of the ASIC are presented as well.
international conference on systems | 2009
Jiri Haze; Radimir Vrba; Michal Pavlik
The article deals with a custom based integrated measurement unit (IMU), which serves as processing device for MEMS based pressure measurement. The IMU consists of the three elementar stages, measurement stage, processing stage and communication stage. They are implemented on the one single board. The measurement block has 16-bit resolution with 64 provided measurement ranges to sutisfy appropriate accuracy. The power supply is 5 V, which allows to measure current with 238 nA step within 1 mA measurement range. The communication stage is based upon I2C standard.
Archive | 2008
Michal Pavlik; Jiri Haze; Radimir Vrba
The area of physical quantity processing in recent sensoric applications demands for high accuracy, low distortion, fast response and low power consumption. There are many physical quantities, which could be processed, mainly pressure, temperature, humidity etc. The pressure processing is one of the most important issues for designers. There exist many problems, which have to be solved i.e. how to measure relative and absolute pressure, how to process signal from sensor with low amplitude, how to withdraw noise and parasitics and so on. The pressure is usually measured using capacitive principle (Lee & Wise., 1982), (Chavan & Wise, 2001), (He et al., 2007). The capacitor is formed by measuring membrane and substrate, see Fig. 1. When the pressure is applied, the membrane is deformed and the distance between membrane and substrate changes. It causes the change of capacity, which is processed in next stages.
2008 International Conference on Advances in Electronics and Micro-electronics | 2008
Michal Pavlik; Jiri Haze; Radimir Vrba
This paper describes the design of the proposed capacity to digital converter. Some important simulations of the converters behavior are presented as well. For capacity value processing second order delta-sigma modulator with input adjusting circuitry was used. The switched current (SI) technique was used in the proposal. It brings small dimensions of the chip and easy integration into the digital circuitry.
international conference on telecommunications | 2015
Michal Pavlik; Vilem Kledrowetz; Marian Pristach; Marek Bohrn; Lukas Fujcik; Jiří Háze
The paper deals with a design of the 16-bit MASH Delta-sigma (ΔΣ) converter utilizing switched capacitor technique (SC). The attention was paid to reach 16bit of ENOB resolution even the same precision of STF in band. This requirement is crucial to evaluation of the signal amplitude independently on its frequency. Multistage structure of two second order CIDIDF modulator was used. The system consists of continuous time amplifier, switched Delta-sigma modulator and decimation digital filter. The ONSemi I3T25 350nm CMOS technology was used for the design. The value of SNDR = 106.5 dB (ENOB = 17.4 bits) was achieved.
international conference on telecommunications | 2013
Michal Pavlik; Vilem Kledrowetz; Jiri Haze; Marian Pristach; Roman Prokop; Lukas Fujcik; Fabian Khateb
The paper deals with a design of the 12-bit sigma delta (ΣΔ) modulator using switched capacitor technique (SC). It is a part of the system for vibration sensor output processing. Processing system consists of pre-amplifier, delta-sigma modulator and decimation digital filter. Detailed description of design process of the ΣΔ modulator is described in article. The design process starts by parameter requirements determination, continuing by structure proposal, design method and coefficients selection, selecting of compensation methods and concluding by design on the chip. ONSemi I2T100 700 nm CMOS technology was used for design. The value of SNDR = 81.1 dB (ENOB = 13.2 bits) was achieved.
IEICE Electronics Express | 2012
Fabian Khateb; Pavel Horsky; Lukas Fujcik; Radimir Vrba; Michal Pavlik
This article deals with investigating research errors and inaccurate results which appear in the article “High performance lowvoltage QFG-based DVCC and a novel fully differential SC integrator based on it” [1] H. Moradzadeh and S. J. Azhari, IEICE Electron. Express, vol. 5, no. 23, pp. 1017–1023, 2008.