Michel Houssa

A Thermally Stable and High-Performance 90-nm

In this paper, we optimize the stack of a 90-nm CMOS-friendly WAl₂O₃Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al₂O₃Cu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400 °C and, on the other, to obtain excellent memory performances. After optimization of the Al₂O₃ layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (0 ns) at low voltage (<;3 V), and low-current (10 μA), and multilevel operation. Finally, 10⁶ cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125 °C.

{\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-¿ deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

-Based 1T1R CBRAM Cell

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm²/Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec

High FET Performance for a Future CMOS

The conduction mechanisms and nature of the filament formed in the low resistive state of TiN/HfO2/TiN resistive random access memories are studied from the temperature-dependence of their current-voltage characteristics. These characteristics are analyzed using the percolation theory of conductor networks, allowing us to extract the temperature-dependence of their effective resistivity. The results suggest a semiconducting-like nature of the filament in these devices. By considering the formation of a large density (about 10 at. %) of oxygen vacancies in HfO2, the electronic properties of such O-deficient HfOx filaments are computed using first-principles calculations. These calculations confirm the likely semiconducting nature of the filament formed in these devices.

\hbox{GeO}_{2}

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm2 at VG=1 V, a peak mobility of 190 cm2/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for VDD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm2/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

-Based Technology

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied At. Layer Deposition (ALD) of high-k dielec. layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidn. in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidn. states lower than 4+. Still, elec. results indicate that small amts. of Ge in oxidn. states lower than 4+ are not detrimental for device performance. Partial intermixing was obsd. for high-k dielec. and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates. [on SciFinder (R)]

Germanium MOSFETs With

Bi-layer gate stacks consisting of a HfO/sub 2/ and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400/spl deg/C due to radical oxygens, leading to an improvement in the quality of HfO/sub 2/ with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO/sub 2/-like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO/sub 2/-like interface demonstrate RPO as a promising way for gate-stack optimization.

\hbox{CeO}_{2}/\hbox{HfO}_{2}/ \hbox{TiN}

A low-temperature (Tu2009u2009=u2009u20091.5-8u2009K) electron paramagnetic resonance study of p-type 2H-polytype natural MoS2 crystals reveals a previously unreported anisotropic signal of corresponding defect density (spin Su2009u2009=u2009u2009½) ~5u2009u2009×u2009u20091014 cm-3. For the applied magnetic field B//c-axis, the response is comprised of a single central asymmetric Zeeman peak at zero-crossing gu2009u2009=u2009u20092.102(1), amid a symmetrically positioned hyperfine doublet of splitting 6.6(2) G. Field angular observations reveal a two-branch g pattern, indicative of a defect of lower than axial symmetry, likely orthorhombic (C 2v). Based on the signal specifics, it is ascribed to a system of decoupled Pb impurities substituting for Mo, the defect operating as an acceptor, with estimated thermal activation energyu2009u2009>10 meV. Supporting theoretical anticipation, the results pinpoint the conduct of the Pb impurity in layered MoS2.

Gate Stacks

In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first-principles calculations with Non-Equilibrium Green functions transport simulations. The intrinsic contact resistivity is found to saturate at ~2x10-10 Ω.cm2 with the doping concentration and sets an intrinsic limit to the ultimate contact resistance achievable for n-doped Si|amorphous-TiSi. This limit arises from the intrinsic properties of the semiconductor and of the metal such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting metals with a heavy electron effective mass helps reducing the interface intrinsic contact resistivity.