Annelies Delabie

Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide

In search of a proper passivation for high-k Ge metal-oxide-semiconductor devices, the authors have deposited high-k dielectric layers on GeO2, grown at 350–450°C in O2. ZrO2, HfO2, and Al2O3 were deposited by atomic layer deposition (ALD). GeO2 and ZrO2 or HfO2 intermix during ALD, together with partial reduction of Ge4+. Almost no intermixing or reduction occurs during Al2O3 ALD. Capacitors show well-behaved capacitance-voltage characteristics on both n- and p-Ge, indicating efficient passivation of the Ge∕GeOx interface. The density of interface states is typically in the low to mid-1011cm−2eV−1 range, approaching state-of-the-art Si∕HfO2∕matal gate devices.

CMOS Process-Compatible High-Power Low-Leakage AlGaN/GaN MISHEMT on Silicon

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si₃N₄/Al₂O₃ bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance <i>R</i>_{on, sp} of 2.9 mΩ·cm². The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

Enhanced initial growth of atomic-layer-deposited metal oxides on hydrogen-terminated silicon

A route is presented for activation of hydrogen-terminated Si(100) prior to atomic layer deposition. It is based on our discovery from in situ infrared spectroscopy that organometallic precursors can effectively initiate oxide growth. Narrow nuclear resonance profiling and Rutherford backscattering spectrometry show that surface functionalization by pre-exposure to 108 Langmuir trimethylaluminum at 300 °C leads to enhanced nucleation and to nearly linear growth kinetics of the high-permittivity gate dielectrics aluminum oxide and hafnium oxide.

Passivation of Ge ( 100 ) ∕ GeO2 ∕ high-κ Gate Stacks Using Thermal Oxide Treatments

The physical and electrical properties of Ge/GeO 2 /high-κ gate stacks, where the GeO 2 interlayer is thermally grown in molecular oxygen, are investigated. The high-K layer (ZrO 2 , HfO 2 , or Al 2 O 3 ) is deposited in situ on the GeO 2 interlayer by atomic layer deposition. Detailed analysis of the capacitance-voltage and conductance-frequency characteristics of these devices provides evidence for the efficient passivation of the Ge(100) surface by its thermal oxide layer. A larger flatband voltage hysteresis is observed in HfO 2 -based gate stacks, as compared to Al 2 O 3 gate stacks, which is possibly related to the more pronounced intermixing observed between the HfO 2 and GeO 2 .

Capacitance-voltage characterization of GaAs–Al2O3 interfaces

The authors apply the conductance method at 25 and 150°C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains.

Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures

The authors show the implications that the free carrier trapping lifetime has on the capacitance-voltage (CV) characterization method applied to metal-oxide-semiconductor (MOS) structures. It is shown that, whereas the CV characterization method for deducing interface state densities works well for Si, the generally used frequency range of 100Hz–1MHz is much less adapted to GaAs MOS structures. Only interface trapping states in very small portions of the GaAs bandgap are measured with this frequency range, and mainly the very important midgap region is not properly probed. Performing an additional measurement at 150°C on GaAs MOS structures eliminates this problem.

Germanium surface passivation and atomic layer deposition of high-k dielectrics?a tutorial review on Ge-based MOS capacitors

Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels). However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance. In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (e.g. epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics. In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures. To further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed.

Electronic structure of GeO2-passivated interfaces of (100)Ge with Al2O3 and HfO2

Analysis of internal photoemission and photoconductivity in Ge/thermal germanium oxide/high-dielectric constant oxide (HfO2,Al2O3) structures reveals that the bandgap of the germanium oxide interlayer is significantly lower (4.3±0.2eV) than that of stiochiometric GeO2 (5.4–5.9eV). As a result, the conduction and valence band offsets at the interface appear to be insufficient to block electron and hole injection leading to significant charge trapping in the GeOx∕high-κ oxide stack. Formation of a hydroxyl-rich Ge oxide phase is suggested to be responsible for the modification of the oxide properties.

Germanium for advanced CMOS anno 2009: a SWOT analysis

Germanium has emerged as an exciting alternative material for high-performance scaled CMOS, however not without difficulties. After a review of the state-of-the-art, mainly focusing on two techniques to passivate the channel/dielectric interface, we analyze the strengths (carrier mobility, band gap), and weaknesses (n-type doping, lattice mismatch and BTBT leakage) of Ge for MOSFETs. We also identify some opportunities and the most important threats for the future of germanium.

Atomic Layer Deposition of Strontium Titanate Films Using Sr ( #2#1Cp ) 2 and Ti ( OMe ) 4

Strontium titanate (STO) is a promising candidate as a high-k dielectric for dynamic random access memory application. STO thin films are deposited by atomic layer deposition using Sr( t Bu 3 Cp) 2 , Ti(OMe) 4 , and H 2 O as precursors. Growth and saturation behavior of STO and binary oxides are evaluated by ellipsometry thickness measurements. The precursor pulse ratio controls the amount of Sr and Ti incorporated in STO films. Stoichiometric SrTiO 3 is characterized by the lowest crystallization temperature and largest refractive index, density, and dielectric constant. An excess of Ti or Sr results in an increase in the crystallization onset temperature and contraction or expansion of the cubic cell constant of perovskite SrTiO 3 . Incorporation of more Sr in STO reduces the leakage current density but also increases the capacitance-equivalent thickness.