Michel Jezequel

On multiple slice turbo codes

The main problem with the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem by using a new family of turbo codes called Multiple Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a constrained interleaver structure that allows the parallel decoding of the P independent codewords in each dimension. The optimization of the interleaver is described. A high degree of parallelism is obtained with equivalent or better performance than thedvb-rcs turbo code. For very high throughput applications, the parallel architecture decreases both decoding latency and hardware complexity compared to the classical serial architecture, which requires memory duplication.RésuméLe problème majeur dans l’implementation matérielle d’un turbo-décodeur réside dans le manque de parallélisme des algorithmes de décodage fondés sur la probabilitéa posteriori maximale (MAP). Cet article propose un nouveau procédé de turbocodage basé sur deux idées : le codage de chaque dimension par P codes convolutifs récursifs circulaires indépendants et l’imposition de contraintes sur la structure de l’entrelaceur de façon à permettre de décoder en parallèle les P codes convolutifs dans chaque dimension. La construction des codes constituants et de l’entrelaceur est décrite et analysée. Un haut degré de parallélisme est obtenu avec des performances équivalentes ou meilleures que le turbocode de la normedvb-rcs. L’architecture parallèle du décodeur permet de réduire à la fois la latence de décodage et la complexité du turbo-décodeur pour des applications à très hauts débits.

Towards Gb/s turbo decoding of product code onto an FPGA device

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup. Based on an innovative architecture which enables the memory blocks between all half-iterations to be removed and clocked at only 37.5 MHz, the turbo decoder processes input data at 600Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmission.

Energy Efficient Turbo Decoder with Reduced State Metric Quantization

In the field of mobile communications, the energy issue of a turbo decoder becomes an equivalent constraint as through-put and performance. This paper describes a technique to reduce the internal bitwidth of the state metrics, and hence, to decrease the entire energy dissipation of a turbo decoder. This approach is based on the saturation of the state metrics. Two cases are investigated: saturation outside the ACS recursion loop and saturation inside the ACS recursion loop. The targeted system is the Universal Mobile Telecommunications System (UMTS) with an 8-state turbo decoder using the Max-Log-MAP algorithm. When received symbols and extrinsic informations are respectively 4-bit and 6-bit quantized, the internal bitwidth of the state metrics can be reduced from 7 bits downto 4 bits. This reduction is paid by a loss of 0.1 dB at a Bit Error Rate (BER) of 1-6. In addition, when 40 SISO decoders perform in parallel, the proposed optimization yields to a reduction of memory area by 10% and leads to an energy reduction of 24% for a 70 nm technology.

ASIP-Based Universal Demapper for Multiwireless Standards

The emergence of diverse wireless standards, employed in various transmission environments, is leading towards evolution of flexible radio platforms. In this letter, we are presenting the first universal Application Specific Instruction-set Processor (ASIP)-based flexible demapper component of a radio platform. The proposed architecture provides full flexibility ranging from low complexity QPSK Gray-mapped constellations to high complexity 256-QAM rotated constellations in turbo demodulation framework. The presented architecture provides the liberty to use this demapper both in iterative and noniterative receivers. Besides flexibility, ASIP synthesis results demonstrate a throughput of 606 Mega LLR per second for 16-QAM Gray-mapped constellation.