Patrick Adde

Towards Gb/s turbo decoding of product code onto an FPGA device

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup. Based on an innovative architecture which enables the memory blocks between all half-iterations to be removed and clocked at only 37.5 MHz, the turbo decoder processes input data at 600Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmission.

Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes

Maximum likelihood soft-decision decoding of linear block codes is addressed in this correspondence. A novel algorithm based on Chase-2 algorithm for the decoding of systematic binary block codes is detailed. A double re-encoding technique in place of the classical algebraic decoding for the computation of the candidate codeword list is the major innovation of the proposed algorithm. This approach has been successfully applied to systematic block codes that have a code rate equal to 1/2 and a parity check matrix composed of an invertible submatrix for the redundancy part. Simulation results show performance close to the optimum maximum likelihood decoding for an excellent tradeoff between BER performance and computational complexity. Then, the challenging issue of designing a decoder for a specific family of short binary block codes, called Cortex codes is also described. Three soft decoders for Cortex codes with lengths equal to 32, 64, and 128 and a code rate equal to 1/2 have been designed. Then, all the decoders were successively implemented onto an field-programmable gate array (FPGA) device. To our knowledge, they are the first efficient digital implementations of Cortex codes.

Block Turbo Code with Binary Input for Improving Quality of Service

An iterative decoding algorithm (“Block Turbo Code (BTC) algorithm”) for product codes based on soft decoding and soft decision output of the component codes was introduced by R. Pyndiah in 1994 [1][2]. It uses the concepts developed by C. Berrou who proposed a technique to encode and decode a class of error correcting codes, called “Turbo codes” CTC [3]. The BTC is based on the product code which is a series concatenated coding scheme, introduced by Elias [4]. The information bits are placed in a matrix. The rows of the matrix are encoded by a linear block code and the columns by a second block code.

Above Gbit/s data transmission using full-parallel block turbo decoder architecture

RésuméCet article présente une nouvelle architecture atteignant de très haut débit pour le turbodécodage de codes produits. Ce type d’architecture est capable de décoder des codes produits reposant sur des codes binaires de type BCH ou des codes m-aire de type Reed Solomon. Son principal atout est qu’elle permet l’élimination des plans mémoires associés aux matrices générées par un code produit entre les différentes demi-itérations pour le turbodécodage. En fait, la solution architecturale que nous détaillons dans ce papier offre de nouvelles opportunités pour l’application des turbocodes dans des systèmes nécessitant des débits supérieurs au Gbit/s comme les systèmes de transmission sur fibre optiqueAbstractThis paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory block between each half-iteration to be removed. In fact, the proposed architecture opens the way to numerous applications such as optical transmission. In particular, our block turbo decoding architecture can support optical transmission at data rates above Gbit/s