Michiari Kawano

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Abstract This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k

Efficient Reduction of Standby Leakage Current in LSIs for Use in Mobile Devices

We propose shallow channel-implants and asymmetric implants as a way to reduce off-state current. The former is effective in reducing sub-threshold leakage for n-type metal–oxide–semiconductor (NMOS), because of compensating for a decrease in B density near the channel surface that borders the shallow trench isolation (STI). The latter is also effective in reducing sub-threshold leakage current and gate-induced drain leakage (GIDL) for NMOS and p-type metal–oxide–semiconductor (PMOS), respectively, because asymmetric implants improve carrier mobility, which allows us to decrease subthreshold leakage without lowering on-state current (Ion), and also relax the high electric field in the drain junction at the edge of the gate. Using the combination of both techniques, we succeeded in reducing static random access memory (SRAM) leakage current by up with 1/10 compared to the control, while maintaining a high speed performance.