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Dive into the research topics where Takumi Hasegawa is active.

Publication


Featured researches published by Takumi Hasegawa.


17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 | 2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; Takumi Hasegawa; Shinobu Okanishi; Hiroshi Yanagita; Shiro Kamohara; Masaru Kadoshima; Keiichi Maekawa; Tomohiro Yamashita; Duc Hung Le; Takumu Yomogita; Masaru Kudo; Kuniaki Kitamori; Shuya Kondo; Yuuki Manzawa

A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.


symposium on vlsi technology | 2014

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Shiro Kamohara; Nobuyuki Sugii; Yoshiki Yamamoto; Hideki Makiyama; Tomohiro Yamashita; Takumi Hasegawa; Shinobu Okanishi; Hiroshi Yanagita; Masaru Kadoshima; Keiichi Maekawa; Hitoshi Mitani; Yasushi Yamagata; Hidekazu Oda; Yasuo Yamaguchi; Koichiro Ishibashi; Hideharu Amano; Kimiyoshi Usami; Kazutoshi Kobayashi; Tomoko Mizutani; Toshiro Hiramoto

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.


Applied Physics Express | 2015

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

Toshitsugu Sakamoto; Munehiro Tada; Yukihide Tsuji; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; Yasuhiro Ogasahara; Hidekazu Oda; Shiro Kamohara; Yasushi Yamagata; Nobuyuki Sugii; Hiromitsu Hada

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34–1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.


international conference on microelectronic test structures | 2015

Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell

Koji Nii; Kenji Yamaguchi; Makoto Yabuuchi; Naoya Watanabe; Takumi Hasegawa; Shoji Yoshida; Takeshi Okagaki; Miho Yokota; Kazunori Onozawa

Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV Vt offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM Vmin for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV Vmin at 250 MHz operation at 25°C and 85°C.


2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII) | 2015

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM

Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; Yasuhiro Ogasahara; Hidekazu Oda; Shiro Kamohara; Yasushi Yamagata; Nobuyuki Sugii; Hiromitsu Hada

We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33-1.2 V operation voltage and 46.8-μA/MHz active current (or 18.26-μW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at 0.54 V and small sleep power (0.628 μW), simultaneously.


symposium on vlsi circuits | 2017

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Makoto Yabuuchi; Koji Nii; Shinji Tanaka; Yoshihiro Shinozaki; Yoshiki Yamamoto; Takumi Hasegawa; Hiroki Shinkawata; Shiro Kamohara

A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.


international conference on ic design and technology | 2017

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive

Takumi Hasegawa; Yoshiki Yamamoto; Hideki Makiyama; Hiroki Shinkawata; Shiro Kamohara; Yasuo Yamaguchi

Ultra low power performance is indispensable for Micro Controller Unit (MCU) used as wireless sensor and communication nodes which needs battery maintenance free and energy harvesting operation in the Internet of things (IoT) era. The Silicon on Thin Buried Oxide (SOTB) is one of the most suitable CMOS technology for ultra low power MCU because of its small variability and back bias controllability. This paper describes the mechanism of ultra low power performance of SOTB, performance demonstration of transistor, SRAM and MCU test chip, and what SOTB will realize for IoT and Automotive. SOTB will have less than 1/10 of power efficiency by low leakage current at standby mode and low current consumption at operation mode which todays technology cannot realize.


IEEE Micro | 2015

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; Hidekazu Oda; Shiro Kamohara; Yasushi Yamagata; Nobuyuki Sugii; Hiromitsu Hada; Yasuhiro Ogasahara

The authors demonstrate an ultra-low-power microcontroller unit (MCU) with an embedded atom-switch ROM, which performs 0.39-V operation voltage and 18.26-pJ/cycle minimum active energy (or 18.26-μW/MHz minimum active power) at 14.3 MHz. The MCU is fabricated using an embedded atom-switch process with a hybrid silicon-on-thin-buried-oxide (SOTB) core and bulk I/O transistors. The atom switch is suitable for an ultra-low-voltage operation because of its high on/off conductance ratio. The SOTB CMOS with a body-bias voltage control realizes a high operation frequency of 40 MHz at 0.54 V and an ultra-low sleep power of 0.628 μW, simultaneously.


Archive | 2016

Semiconductor integrated circuit device and wearable device

Shiro Kamohara; Yasushi Yamagata; Takumi Hasegawa; Nobuyuki Sugii


Archive | 2015

Semiconductor device with mode designation and substrate bias circuits

Shiro Kamohara; Yasushi Yamagata; Takumi Hasegawa; Nobuyuki Sugii

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Nobuyuki Sugii

Tokyo Institute of Technology

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