Michio Yotsuyanagi

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology. >

A CMOS 50% duty cycle repeater using complementary phase blending

The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

The authors describe a 10-b, 100-Ms/s ADC (analog-to-digital converter) with a pipelined subranging scheme, a sample-and-hold amplifier with 7.6-ns acquisition time, and a 94-dB, 335-MHz op amp, enabling it to operate with 950-mW power dissipation from a single -5 V power supply. The design consists of sample-and-hold amplifiers, a coarse 6-b flash ADC, a fine 5-b flash ADC, a digital-to-analog converter, an analog subtractor, a register, and a digital adder with an error-correction function. The ADC is fabricated using a 0.8- mu m BiCMOS process featuring a double-layer polysilicon capacitor. The signal-to-noise-plus-distortion ratio as a function of input frequency at a 100-Ms/s conversion rate is shown. >

A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous binary tree-type demultiplexer and frequency conversion architecture

A single-chip 4.25 Gb/s 32:1, 1:32 transceiver, meeting the emerging ANSI fiber channel (FC) standard, uses 0.25 /spl mu/m CMOS technology. To achieve 4.25 Gb/s operation, the features include: 1) an asynchronous tree-type 1:8 demultiplexer (DEMUX), 2) an 8 b to 10 b parallel-to-parallel frequency converter, and 3) comma-detection and word-alignment logic. The transceiver consumes 600 mW in 4.25 Gb/s operation with a 2.5 V supply. Higher-speed operation that that of a previous CMOS FC design is achieved.

A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock

We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phase detector for a PLL clock recovery circuit (CRC) and a root module for an asynchronous tree-type DEMUX. Using a new combined CRC-DEMUX structure, we achieved 6 Gbps 1:8 DEMUX with CRC using a 0.18 /spl mu/m CMOS in 83 mW power consumption.

A 20 Gb/s CMOS multi-channel transmitter and receiver chip set for ultra-high resolution digital display

The digital display interface for an ultra-high resolution flat panel (3200/spl times/2400-pixels) requires 16 Gb/s bandwidth; moreover, 20 Gb/s is required when using an 8B10B encoder to increase serial data transmission accuracy. Low power consumption and low cost are also essential for consumer applications. These requirements are supported by multi-channel transmission, such as four 5 Gb/s CMOS LSIs, which is an effective approach to achieving an aggregate bandwidth of 20 Gb/s. There are two system problems in developing a multi-channel transmitter (TX) and receiver (RX) LSIs. One is the phase difference between multiple chips due to the data skew caused by differences between transmission cable lengths. The other is the frequency difference between the TX and RX system clocks. In response to these problems, we have developed compensation technology featuring the use of an elastic buffer for both the phase and frequency differences. Moreover, to achieve 6 Gb/s operation, a self-alignment phase detector with parallel output for a high-speed clock and data recovery circuit (CDR) and a 500 MHz fully pipelined 8B10B encoder are developed.

A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter

We have developed a 2 V, 10 b, 20 MS/s, mixed-mode (voltage-mode and current-mode) subranging CMOS A/D Converter (ADC) suitable for video-signal processing systems. Its 2 V supply voltage and 20 mW power consumption are lower than those of any other video-rate ADC reported to date. This ADC employs voltage-mode circuitry for coarse 5 b A/D conversion and current-mode circuitry for fine 6 b A/D conversion. In addition to this mixed-mode subranging architecture, a newly developed differential comparator and a new current-tree A/D conversion architecture also contribute to the achievement of high speed at low supply voltage.

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications

A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-/spl mu/m CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3/spl times/2 mm/sup 2/, and the power dissipation is 860 mW.

An advanced 0.25-/spl mu/m BiCMOS process integration technology for multi-GHz communication LSIs

This paper presents an advanced BiCMOS process integration technology, which employs 0.25-/spl mu/m Ti salicide p/sup +//n/sup +/ dual gate CMOSFETs, double poly-Si self-aligned bipolar transistors and passive elements such as double poly-Si capacitors and poly-Si resistors, while reducing the number of process steps. We also have demonstrated a one-chip transceiver LSI circuit for an optical data link using the ANSI fiber-channel standard of 4.25 Gb/s. The voltage controlled oscillator (VCO) of the clock recovery circuit oscillates from 3.2 GHz to 6.8 GHz according to the control voltage.

A CMOS imager with new focal-plane motion detectors

A CMOS imager with new focal-plane motion detectors has been developed as the front-end of vision systems. The chip generates both a normal video signal and a local image signal; i.e. the local area where the motion is detected is automatically scanned. Key technologies include a unity-gain two-port pixel, sparsely-placed motion detectors, and a multistage column readout circuit. A 5.8/spl times/8.7 mm/sup 2/ chip fabricated by using 0.35 /spl mu/m CMOS process contains 192/spl times/192 pixels and 7/spl times/7 motion detectors.