Muneo Fukaishi

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

12Gb/s duobinary signaling with /spl times/2 oversampled edge equalization

A backplane transceiver in 90 nm CMOS that employs duobinary signaling over copper traces is described. To introduce duobinary signaling into data transfers on printed boards, three techniques are developed: 1) edge equalization for equalizer adaptation; 2) 2/spl times/ oversampled transmitter equalizer for ISI control; and 3) 2b-transition-ensure encoding for clock recovery.

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.

A CMOS 50% duty cycle repeater using complementary phase blending

The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.

A 0.13-/spl mu/m CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the performance of a system enhanced with LSI technology scaling. This is because large frequency-dependent attenuation results in poor eye-opening performance and a high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-m 28AWG cable transceiver fabricated by using 0.13-/spl mu/m CMOS technology. In this transceiver, a continuous-time post-equalizer, with recently developed no-feedback-loop high-speed analog amplifiers, can handle up to 9dB of frequency-dependent attenuation in cables and also achieve an 18-dB improvement in the attenuation (27dB total improvement) by using pre- and post-equalization techniques in combination.

A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

A 30-MHz-2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5-8-dB noise figure, a -11-dBm in-band third-order intercept point, and a +38-dBm second-order intercept point while drawing only 25-37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2-30-MHz detection bandwidth, -83-dBm minimum sensitivity, and a 29-48-dB DR was demonstrated.

A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous binary tree-type demultiplexer and frequency conversion architecture

A single-chip 4.25 Gb/s 32:1, 1:32 transceiver, meeting the emerging ANSI fiber channel (FC) standard, uses 0.25 /spl mu/m CMOS technology. To achieve 4.25 Gb/s operation, the features include: 1) an asynchronous tree-type 1:8 demultiplexer (DEMUX), 2) an 8 b to 10 b parallel-to-parallel frequency converter, and 3) comma-detection and word-alignment logic. The transceiver consumes 600 mW in 4.25 Gb/s operation with a 2.5 V supply. Higher-speed operation that that of a previous CMOS FC design is achieved.

A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock

We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phase detector for a PLL clock recovery circuit (CRC) and a root module for an asynchronous tree-type DEMUX. Using a new combined CRC-DEMUX structure, we achieved 6 Gbps 1:8 DEMUX with CRC using a 0.18 /spl mu/m CMOS in 83 mW power consumption.