Miguel Muñoz Rojo

Energy Dissipation in Monolayer MoS2 Electronics

The advancement of nanoscale electronics has been limited by energy dissipation challenges for over a decade. Such limitations could be particularly severe for two-dimensional (2D) semiconductors integrated with flexible substrates or multilayered processors, both being critical thermal bottlenecks. To shed light into fundamental aspects of this problem, here we report the first direct measurement of spatially resolved temperature in functioning 2D monolayer MoS2 transistors. Using Raman thermometry, we simultaneously obtain temperature maps of the device channel and its substrate. This differential measurement reveals the thermal boundary conductance of the MoS2 interface with SiO2 (14 ± 4 MW m-2 K-1) is an order magnitude larger than previously thought, yet near the low end of known solid-solid interfaces. Our study also reveals unexpected insight into nonuniformities of the MoS2 transistors (small bilayer regions) which do not cause significant self-heating, suggesting that such semiconductors are less sensitive to inhomogeneity than expected. These results provide key insights into energy dissipation of 2D semiconductors and pave the way for the future design of energy-efficient 2D electronics.

Low Variability in Synthetic Monolayer MoS2 Devices

Despite much interest in applications of two-dimensional (2D) fabrics such as MoS2, to date most studies have focused on single or few devices. Here we examine the variability of hundreds of transistors from monolayer MoS2 synthesized by chemical vapor deposition. Ultraclean fabrication yields low surface roughness of ∼3 Å and surprisingly low variability of key device parameters, considering the atomically thin nature of the material. Threshold voltage variation and very low hysteresis suggest variations in charge density and traps as low as ∼1011 cm-2. Three extraction methods (field-effect, Y-function, and effective mobility) independently reveal mobility from 30 to 45 cm2/V/s (10th to 90th percentile; highest value ∼48 cm2/V/s) across areas >1 cm2. Electrical properties are remarkably immune to the presence of bilayer regions, which cause only small conduction band offsets (∼55 meV) measured by scanning Kelvin probe microscopy, an order of magnitude lower than energy variations in Si films of comparable thickness. Data are also used as inputs to Monte Carlo circuit simulations to understand the effects of material variability on circuit variation. These advances address key missing steps required to scale 2D semiconductors into functional systems.

Spatially Resolved Thermometry of Resistive Memory Devices

The operation of resistive and phase-change memory (RRAM and PCM) is controlled by highly localized self-heating effects, yet detailed studies of their temperature are rare due to challenges of nanoscale thermometry. Here we show that the combination of Raman thermometry and scanning thermal microscopy (SThM) can enable such measurements with high spatial resolution. We report temperature-dependent Raman spectra of HfO2, TiO2 and Ge2Sb2Te5 (GST) films, and demonstrate direct measurements of temperature profiles in lateral PCM devices. Our measurements reveal that electrical and thermal interfaces dominate the operation of such devices, uncovering a thermal boundary resistance of 28u2009±u20098 m2K/GW at GST-SiO2 interfaces and an effective thermopower 350u2009±u200950 µV/K at GST-Pt interfaces. We also discuss possible pathways to apply Raman thermometry and SThM techniques to nanoscale and vertical resistive memory devices.

Thermal transport across graphene step junctions

Step junctions are often present in layered materials, i.e. where single-layer regions meet multi-layer regions, yet their effect on thermal transport is not understood to date. Here, we measure heat flow across graphene junctions (GJs) from monolayer to bilayer graphene, as well as bilayer to four-layer graphene for the first time, in both heat flow directions. The thermal conductance of the monolayer-bilayer GJ device ranges from ~0.5 to 9.1x10^8 Wm-2K-1 between 50 K to 300 K. Atomistic simulations of such GJ device reveal that graphene layers are relatively decoupled, and the low thermal conductance of the device is determined by the resistance between the two dis-tinct graphene layers. In these conditions the junction plays a negligible effect. To prove that the decoupling between layers controls thermal transport in the junction, the heat flow in both directions was measured, showing no evidence of thermal asymmetry or rectification (within experimental error bars). For large-area graphene applications, this signifies that small bilayer (or multilayer) islands have little or no contribution to overall thermal transport.