Mihailo Isakov

PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures

In this paper, we introduce a neural network based predictive routing algorithm for on-chip networks which uses anticipated global network state and congestion information to efficiently route network traffic. The core of the algorithm is a multi-layer neural network machine learning approach where the inputs are level of occupancy of virtual channels, average latency for a particular router to be selected for route computation, the probability of virtual channel allocation, and the probability of winning switch arbitration at the crossbar. The algorithm lends itself to both node routing and source routing. To evaluate the PreNoc routing algorithm, we simulate both synthetic traffic and real application traces using a cycle-accurate simulator. In most test cases, the proposed approach outperforms current deterministic and adaptive routing techniques in terms of latency and throughput. The hardware overhead for supporting the new routing algorithm is minimal.

A secure and robust scheme for sharing confidential information in IoT systems

Abstract In Internet of Things (IoT) systems with security demands, there is often a need to distribute sensitive information (such as encryption keys, digital signatures, or login credentials etc.) to the devices, so that it can be retrieved for confidential purposes at a later moment. However, this piece of information cannot be entrusted to any individual device, since the malfunction of one device will jeopardize the security of the entire network. Even if the information is split among the devices, there is still a danger when attackers compromise a group of them. Therefore we have designed and implemented a secure and robust scheme to facilitate the sharing of sensitive information in IoT networks. This solution provides two important features: 1) This scheme uses Threshold Secret Sharing (TSS) to split the information into shares to be kept by all devices in the system. And so the information can only be retrieved collaboratively by groups of devices. 2) This scheme ensures the privacy and integrity of that piece of information even when there is a large amount of sophisticated and collusive attackers who can hijack the devices. It is able to identify all the compromised devices, while still keeping the secret unknown and unforgeable to attackers.

Designing Secure Heterogeneous Multicore Systems from Untrusted Components

In current systems-on-chip (SoCs) designs, processing elements, i.e., intellectual property (IP) cores, may come from different providers, and executable code may have varying levels of trust, all executing on the same compute platform and sharing resources. This creates a very fertile attack ground and represents the Achilles’ heel of heterogeneous SoC architectures and distributed connected devices. The general consensus today is that conventional approaches and software-only add-on schemes fail to provide sufficient security protections and trustworthiness. In this paper, we develop a secure heterogeneous SoC architecture named Hermes. It represents a new architectural model that integrates multiple processing elements (called tenants) of secure and non-secure cores into the same chip design while: (a) maintaining individual tenant security; (b) preventing data leakage and corruption; (c) promoting collaboration among the tenants; and (d) tolerating untrusted tenants with potentially malicious purposes. The Hermes architecture is based on a programmable secure router interface and a trust-aware routing algorithm. Depending on the trust levels of computing nodes, it is able to virtually isolate them in different access modes to the memory blocks. With secure key management and join protocols, Hermes is also able to function properly when nodes request for, or allow, memory access in a dishonest manner. With 17% hardware overhead, it enables the implementation of processing-element-oblivious secure multicore systems with a programmable distributed group key management scheme. The Hermes architecture is meant to emblematize the design of secure heterogeneous multicore computing systems out of unsecured or untrusted components using user-defined security policies to create at the hardware-level virtual zones to enforce these security and trust policies.

Adaptive Manycore Architectures for Big Data Computing

This work presents a cross-layer design of an adaptive manycore architecture to address the computational needs of emerging big data applications within the technological constraints of power and reliability. From the circuits end, we present links with reconfigurable repeaters that allow single-cycle traversals across multiple hops, creating fast single-cycle paths on demand. At the microarchitecture end, we present a router with bi-directional links, unified virtual channel (VC) structure, and the ability to perform self-monitoring and self-configuration around faults. We present our vision for self-aware manycore architectures and argue that machine learning techniques are very appropriate to efficiently control various configurable on-chip resources in order to realize this vision. We provide concrete learning algorithms for core and NoC reconfiguration; and dynamic power management to improve the performance, energy-efficiency, and reliability over static designs to meet the demands of big data computing. We also discuss future challenges to push the state-of-the-art on fully adaptive manycore architectures.

Janus: An uncertain cache architecture to cope with side channel attacks

Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. In this work, we propose a new cache architecture, called Janus, to enable crypto-systems to introduce randomization and uncertainty in their runtime timing behavior and power utilization profile. In the proposed cache architecture, each data block is equipped with an on-off flag to enable/disable the data block. The Janus architecture has two special instructions in its instruction set to support the on-off flag. Beside the analytical evaluation of the proposed cache architecture, we deploy it in an ARM-7 processor core to study its feasibility and practicality. Results show a significant variation in the timing behavior across all the benchmarks. The new secure processor architecture has minimal hardware overhead and significant improvement in protecting against power analysis and timing behavior attacks.

Advertiser elevator: A fault tolerant routing algorithm for partially connected 3D Network-on-Chips

In this paper, we propose an adaptive routing algorithm for vertically partially connected 3D NoCs to (1) overcome failures in vertical links, and (2) find the nearest available vertical link for rerouting of packets. To track the position of each vertical link and distance to the other nodes, the proposed routing algorithm, named Advertiser Elevator, indexes each vertical link and implements a mechanism for announcing and sharing these indexes with the other nodes of the network. Packets are routed toward the nearest vertical link based on received indexes. The routing algorithm tolerates vertical link failures by interpreting the absence of index messages from a vertical link node as a link failure at the node. Packets are rerouted around failed links based on collected messages. The performance of the Advertiser Elevator routing algorithm is evaluated using the Access Noxim NoC simulator under different network congestion levels and fault rates. The results show that the proposed routing algorithm (1) is able to deliver packets as long as there are at least four live vertical links in the network (e.g., corner links) and (2) improves the average network latency by 15% over the well-known Elevator-First routing algorithm.

Hermes: Secure heterogeneous multicore architecture design

The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a number of significant security challenges. The current trend in SoC design is system-level integration of heterogeneous technologies consisting of a large number of processing elements such as programmable RISC cores, memory, DSPs, and accelerator function units/ASIC. These processing elements may come from different providers, and application executable code may have varying levels of trust. Some of the pressing architecture design questions are: (1) how to implement multi-level user-defined security; (2) how to optimally and securely share resources and data among processing elements. In this work, we develop a secure multicore architecture, named Hermes. It represents a new architectural framework that integrates multiple processing elements (called tenants) of secure and non-secure cores into the same chip design while (a) maintaining individual tenant security, (b) preventing data leakage and corruption, and (c) promoting collaboration among the tenants. The Hermes architecture is based on a programmable secure router interface and a trust-aware routing algorithm. With 17% hardware overhead, it enables the implementation of processing-element-oblivious secure multicore systems with a programmable distributed group key management scheme.