Mike Killian

Chip verification of 4 Mbit DRAMs by e-beam testing

Abstract Due to their high level of integration, dynamic random access memories (DRAMs) place vigorous requirements on the tools needed for internal signal analysis. In this regard, electron-beam testing proves an invaluable analysis tool for design and process optimization. The e-beam tester described here enables testing of a 4 Mbit DRAM, as well as of the future generation which will utilize submicron interconnections. Major development effort has been carried out with respect to the electron optics to fulfill the required e-beam tester performance. Other important verification criteria include the associated test hardware and degree of CAD integration, as well as improved circuit layout for e-beam testability at chip level. Typical 4 Mbit DRAM verification procedures will be outlined: basic logic verification, graphical comparison of simulated and measured signals by CAD integration and precision waveform measurements being the main topics. Finally, future demands will be discussed.