Thomas Vogelsang
Infineon Technologies
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Publication
Featured researches published by Thomas Vogelsang.
international solid-state circuits conference | 2004
J. Kennedy; Robert M. Ellis; James E. Jaussi; Randy Mooney; S. Borkar; Jung-Hwan Choi; Jae-Kwan Kim; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; Jochen Hoffmann; Wolfgang Hokenmaier; R. Houghton; Thomas Vogelsang
We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.
Archive | 2006
Thomas Vogelsang
Archive | 2007
Thomas Vogelsang
Archive | 2001
Manfred Reithinger; Michael A. Killian; Gerd Frankowsky; Oliver Kiehl; Gerhard Mueller; Ernst Stahl; Hartmud Terletzki; Thomas Vogelsang
Archive | 2005
Thomas Vogelsang
Archive | 2003
Thomas Vogelsang
Archive | 2010
Thomas Vogelsang
Archive | 2005
Thomas Vogelsang
Archive | 2004
Manfred Reithinger; Michael A. Killian; Gerd Frankowsky; Oliver Kiehl; Gerhard Mueller; Ernst Stahl; Hartmud Terletzki; Thomas Vogelsang
Archive | 2007
Robert Baxter; Roland Barth; Steve Bowyer; Jonghee Han; Harald Lorenz; Jason Varricchione; Thomas Vogelsang