Mike W. T. Wong

Non‐linear analog circuit fault diagnosis with large change sensitivity

Large change sensitivity has been proved efficient at, but restricted to, generating a linear circuit fault dictionary. This paper discusses the extension of large change sensitivity to non-linear analog circuit fault diagnosis. The fault dictionary is divided into d.c. and a.c. sections. In the d.c. domain, non-linear components are approximated with piecewise linear models. By relating the operating region of each piecewise linear model to the magnitude of a single fault in a procedure termed preconditioning, it is shown that large change sensitivity can efficiently compute the response of a faulty non-linear circuit. Results presented of an analysis of computational complexity show a significant reduction in the cost of simulating single linear resistor faults in a non-linear circuit using this method. In addition, after establishing that the resistive portion of the circuit is fault free, a fault dictionary is constructed for dynamic components using large change sensitivity in the small signal a.c. domain. Included with a discussion on the issues of large change sensitivity based simulation-before-test, a small non-linear circuit is used to demonstrate the effectiveness of the proposed fault diagnosis algorithm. Copyright

Efficient multifrequency analysis of fault diagnosis in analog circuits based on large change sensitivity computation

In this paper we present a method for the optimal selection of test points and the generation of test frequencies. Our method is based on large change sensitivity analysis with element level analysis operating in the frequency domain. The fact that the deviation of individual components can be set to arbitrary value ranging from zero to infinity high fault coverage and enhancement in the overall circuit testability are ensured. The proposed method can diagnose both catastrophic and parametric faults. Our results show that both single and multiple faults can be located within small to medium size circuits. The computation is realized by combining the evaluation before test with a symbolic math package. This combination provides low computational cost and proves to be efficient comparing to conventional fault diagnosis methods.

Enhancing the fault diagnosis of linear analog circuit steady-state DC testing through the analysis of equivalent faults

Presented is a study of fault equivalence in steady-state DC linear analog circuits. Equivalent fault relationships attributable to node isolation or equivalence in the driving-point and/or transfer characteristics of one-port network are shown to prevent effective fault diagnosis in a number of basic analog circuits. The analysis of these conditions using graph and transformation theorems is demonstrated to provide the basis for a more systematic approach to improving fault diagnosis.

Analog circuit equivalent faults in the D.C. domain

Analog circuit faults that produce indistinguishable test measurements are equivalent. Such faults cannot be diagnosed, since they defy fault location and/or value determination. In current simulation-before-test methods equivalent faults are found by inspecting fault simulation data. This approach is unsatisfactory for usually it imparts little information on which aspects of a circuits design lead to equivalent faults or how diagnosis is to be improved. Presented is an examination of a subset of d.c. domain equivalent faults in steady-state linear analog circuits. The proposed methods for equivalent fault identification are aimed at increasing a test engineers understanding of the faulty circuits behaviour beyond that given by data analysis. Ways in which test design benefits from equivalent fault information are also discussed.

Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis

Fault-tolerant design of analog circuits is more difficult than that of digital circuits. Chatterjee has proposed a continuous checksum-based technique to design fault-tolerant linear analog circuits. However, hardware overhead of the embedded checker is an important issue in this technique, which has never been addressed before. This paper proposes an algorithm for reduction of hardware overhead in the checker. Without changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead. As the basis of the algorithm, a serial of theoretic results, including the concept and existence conditions of all-non-zero solutions, have also been presented to verify the algorithm.

On concurrent multiple error diagnosability in linear analog circuits using continuous checksum

Although most of the work done in fault tolerance is in the digital field, it is widely understood that error detection and correction capability in analog circuits has the same importance as in digital circuits. The technique proposed by Abhijit Chatterjee can realize concurrent single error detection and correction in linear analog circuits well. Based on his work, this paper addresses concurrent multiple error detection and correction in linear analog systems, which is known to be a difficult and unsolved problem. We prove that the concurrent error diagnosis scheme using continuous checksum can not be extended to the case of multiple errors under the assumption that the checker and the functional block will not fail simultaneously, though people are still attempting to make such an extension.

A pre-simulation measure of d.c. design-for-testability fault diagnosis quality

Equivalent faults inhibit fault diagnosis by producing indistinguishable test metric measurements. Removal of conditions causing the equivalence in response exhibited by such faults is necessary, if fault diagnosis quality is to be improved. As Design for-Testability (DFT) methodology aims to deliver a degree of fault diagnosis substantially greater than that obtainable testing unassisted by on-chip test specific hardware, designing a DFT scheme with minimal fault equivalence is an issue to be addressed. Presented is a set of simple and inexpensive tests, applied pre-simulation, for identifying catastrophic resistive component faults that cause numerical equivalent d.c. test model responses. Using a biquadratic notch filter modified with a novel DFT scheme, we demonstrate that equivalent fault information is a useful initial measure for assessing the potential increase in fault diagnosis quality obtainable with a DFT scheme.

Feasibility and effectiveness of the algorithm for overhead reduction in analog checkers

Self-checking in analog circuits is more difficult than in digital circuits. The technique proposed by A. Chatterjee (1993) can address concurrent error detection and correction in linear analog circuits and hence the reliability of the original circuit is greatly improved. However, hardware overhead is an important issue in this technique, which has never been addressed before. This paper proposes an algorithm for reduction of hardware overhead in the analog checker, and also presents a series of theoretical results, including the concept of all-non-zero solutions and several existence conditions of such solutions. As the basis of the algorithm, these results are new in the mathematical world and can be used to verify the feasibility and effectiveness of the algorithm. Without changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead.<<ETX>>

DC nonlinear circuit fault simulation with large change sensitivity

Recently a method was proposed for using Large Change Sensitivity (LCS) for DC nonlinear circuit fault simulation. This allowed the advantages of LCS, namely computational efficiency and exactness of solution, to become available for nonlinear circuit Simulation-Before-Test fault diagnosis. This paper improves on that work by further reducing the computational effort in calculating the LCS of nonlinear circuit faults and generalising the algorithm to handle circuits of multiple nonlinear components. Faults are restricted to single catastrophic or parametric linear component faults.

Analog and mixed-signal IP cores testing

This paper, describes a test approach for Intellectual Property (IP) analog or mixed-signal cores, which may be used in core-based System-on-Chip (SOC) designs. The proposed method comprises a two-phase test design process. Given an analog/mixed-signal IP core, an equivalent fault analysis is carried out in the initial phase. The main aim is to extract useful insights for improving the BIST and DfT designs which to be conducted in the second phase. An early built-in self-test (BIST) method was able to achieve high fault coverage comparable to the traditional scan techniques. In the second phase, we propose to apply an improved version of this method based on the weighted sum of selected node voltages. Besides high fault coverage, the proposed BIST technique only needs an extra testing output pin and only a single DC stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for the testing environment of IP cores.