Yinghua Min

IDDT Testing versus IDDQ Testing

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This letter presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.

Test power optimization techniques for CMOS circuits

Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.

Reduction of Number of Paths to be Tested in Delay Testing

Delay testing is important for high speed ICs. The main difficulty in delay testing comes from the huge number of paths and the large percentage of delay untestable paths. Therefore, it is critical to reduce the number of paths to be tested in delay testing. This paper presents two approaches to delay testing with significant reduction of number of paths to be tested, which provide high path delay fault coverage by testing a small number of paths. In the first approach, it is necessary to sample the primary output twice, one before and another after the transition for each test pair. The second approach is by means of accurate measurement of delays of very limited number of paths. In order to make this approach feasible, the paper also introduces a new concept of path sensitization, termed single-transition sensitization, to allow direct measurement of propagation delay of those paths. The paper presents how to select the very limited number of paths, termed sample paths, and how to generate test pairs and observation times for the sample paths for the first approach. On the other hand, it is noted for the second approach that under the analytical delay model (Proc. 9th International Conf. on VLSI Design, Bangalore, India, Jan. 1996, pp. 162–165), most of the paths are delay testable, which makes the accurate measurement approach feasible. In fact, it would be very difficult to select sample paths based on single path sensitization as it was done in (IEEE Trans. on Computers, Vol. c-29, No. 3, pp. 235–248, March 1980). The paper shows that the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths.

Memory efficient ATPG for path delay faults

A memory efficient test pattern generator for path delay faults, DTPG, is presented in this paper, which uses the efficient path identifier to represent a path. A compact bit table, path information table, is proposed to store test information efficiently. Furthermore, DTPG is capable of identifying functional sensitizable paths, which account for large percent of paths in many circuits. The experimental results show that DTPG is memory efficient. It generates tests for C3540 with 57 million paths and preserves the testability information for all paths. Experimental results show the influence of stepwise mandatory sensitization, multiple backtrace, and backtracking limits on the cpu time consumed by delay test generation process.

A novel RTL behavioral description based ATPG method

The paper proposes a novel ATPG (Automatic Test Pattern Generation) method based on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware Description Language). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptions to Process Controlling Trees (PCT) and Data Dependency Graphs (DDG), which are used for behavioral simulation and data tracing. Transfer faults are extracted from DDG edges, which compose a fault set needed for test generation. Then, simulation begins without specifying inputs in advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally, when the simulation ends, the partially fixed input sequence is the generated test sequence. The proposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to cover uncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests with good quality. Experimental results demonstrate that the proposed method is better than ARTIST in three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length, is shorter by 52%; and (3) the fault coverage is higher by 0.89%.

An approach to RTL fault extraction and test generation

The paper presents an approach to fault extraction and test generation at RTL (register transfer level). The proposed ATPG (automatic test pattern generation) is targeting to cover all the extracted faults rather than a specific fault, and based on simulation with unspecified inputs. It uses a request-echo strategy called X-Pulling to greatly reduce the unnecessary backtrack and implication, which makes the algorithm very efficient. Experimental results demonstrate that our approach is better than ARTIST in three aspects: on average, the CPU time is shorter by three orders of magnitude, the test length is shorter by 52% and the fault coverage is higher by 0.89%.

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects

With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead.

An RT-level ATPG based on clustering of circuit states

This paper introduces a new technique employed in a test generation system, ATCLUB, at RT-level, based on clustering of circuit states. States or some sets of states in a low-level description are mapped to high levels in terms of a particular variable in a behavioral description, and termed behavioral phases. Further clustering of behavioral phases is performed to represent the function of a circuit more explicitly and refinedly. Such a refined representation is then used in the test generation algorithm to simplify and speed up search process of test sequences. Experimental results demonstrate the computational efficiency of the clustering process and test pattern generation.

Clustering of behavioral phases in FSMs and its applications to VLSI test

This paper presents a new level of description between behavioral and state descriptions of a finite-state machine (FSM). The description is termed behavioral phase clustering description. New concepts of behavioral phase and clustering of behavioral phases in an FSM are introduced. The new description simplifies functional analysis, verification and test of FSM designs. If an FSM is described at low level, some states can be clustered into behavioral phases directly. If it is described at behavioral level, behavioral phases can be extracted from the behavioral description, and clustering of behavioral phases can be performed through easy functional analysis. As one application of behavioral phase clustering descriptions, a new technique employed in a test generation system, ATCLUB, at Register Transfer (RT)-level based on a behavioral phase transition fault model is introduced in this paper. In ATCLUB, test generation process is accelerated through clustering of behavioral phases. Experimental results show that ATCLUB generates test sequence efficiently, with a sharp decrease in vector count at the penalty of a slightly decrease in fault coverage comparing to other ATPG tools.

Reducing power dissipation during at-speed test application

Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.