Milomir Šoja

A modified dual current mode control method with an adaptive current bandwidth

Summary In this paper, a new adaptive dual current mode control method (ADCMC) is presented, being a result of the modification of existing dual current mode control (DCMC) by introducing an adaptive current bandwidth. The ADCMC offers several important advantages over DCMC, such as no peak-to-average error in the inductor current, better transient response of current loop, and improved line regulation. A detailed analysis of the proposed ADCMC is performed for three types of DC–DC power electronics converters: buck, boost, and non-inverting buck–boost converter. The performances of the ADCMC are tested with simulations and experiments. The obtained results confirm the analysis and validity of the proposed ADCMC method. Copyright

Closed Control Loop Implementation for Single Robot Axis on FPGA Platform

This paper deals with closed control loop implementation for robot single axis with DC motor on FPGA platform. Controlling algorithm is designed in Matlab/Simulink environment and its Custom Toolbox is specifically designed for the purpose of control structures development in real time. Torque is calculated on FPGA structure and brought to a motor which generates necessary PMW. On the motor axis is a pendulum which follows default trajectory. It is a stream of data obtained by calculating or recording robot axis position while moving it manually. Experimental results are also provided.

Analysis of single-phase PLL with novel two-phase generator for grid-connected converters

It is very important for proper work of grid-connected converters to have accurate detection of phase angle, frequency and amplitude of grid voltage. Estimation of these grid parameters can be achieved using PLL (phase locked loop) based on SRF (synchronous reference frame) theory. This PLL should have robustness against noise and offset introduced by measurement and data conversion. This paper proposes an improved PLL alorithm that has excellent noise and offset rejection property. The main part of the proposed PLL is a novel two-phase generator which is used to obtain two quadrature signals for SRF block and PI regulator in closed control loop.

Adaptive delay bank filter for selective elimination of harmonics in SRF-PLL structures

This paper proposes the usage of adaptive delay bank (ADB) based on cascaded delayed signal cancellation (CDSC) structure for selective elimination of the harmonics in the synchronous reference frame phase locked loop (SRF-PLL) structures. The ADB is inserted inside the SRF-PLL structure and it is frequency adaptive, which is the advantage over CDSC structures which are used in PLL as pre-filters, not being adaptive at all. Detailed mathematical analysis and simulation results confirmed suggested method for selective harmonic elimination in PLL.

Experimental verification of single-phase PLL with novel two-phase generator for grid-connected converters

For proper work of grid-connected converters it is important to have accurate detection of phase angle, frequency and amplitude of grid voltage. Estimation of these grid parameters can be achieved using PLL (phase locked loop) based on SRF (synchronous reference frame) theory. This PLL should have robustness against noise and offset introduced by measurement and data conversion. This paper proposes an improved PLL algorithm that has excellent noise and offset rejection property. The main part of proposed PLL is a novel two-phase generator which is used to obtain two quadrature signals for SRF block and PI regulator in closed control loop. Performances of proposed PLL are verified through experimental results given in this paper.

Unipolar switched bidirectional bridgeless power factor correction boost rectifier with adaptive dual current mode control

This paper proposes an application of adaptive dual current mode control (ADCMC) on bidirectional bridgeless power factor correction (BBPFC) boost rectifier with unipolar switching. The given simulation results confirm the benefits of the proposed control strategy of the BBPFC converter, primarily regarding the maintaining of the sine waveform of the average inductor current.

Analysis of discrete VS-PLL structure used for grid parameters estimation

Phase-locked loops (PLLs) are doubtless the most popular synchronization technique in the power converters. Almost all proposed PLL structures known in literature are inherently nonlinear and can be linearized as second order linear time invariant system. Nonlinear nature of PLLs degrades their performances, and question arises if there exist an enhanced PLL structure that would have superior performances. In this paper we propose an three-phase nonlinear PLL structure based on sliding mode control theory and it is named variable structure PLL (VS-PLL). In order to implement this structure on an digital platform, fixed point mapping is performed and corresponding VHDL code is generated by MATLAB HDL coder. Excellent behaviors of continuous and discrete form VS-PLL structure in steady and transient states are confirmed by simulations.

Analysis of discretization methods applied on DC-SOGI block as part of SRF-PLL structure

Phase Locked Loop (PLL) is wide used for grid parameters estimation, as well for grid-converters synchronization. Key block at single-phase Synchronous Reference Frame PLL (SRF-PLL) structure is two-phase generator which is used for generation of two quadrature signals, which are necessary for SRF block. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. In this paper is described second order generalized integrator (SOGI) which is capable to fully reject DC offset and noise which could appear in measured input grid voltage. This two-phase generator is named DC-SOGI. Analog DC-SOGI is made of two second order filters. While these structures are mostly digitally implemented, then it is interesting to analyze discretization method and sampling time impact on two-phase generator. Simulation results confirm given assumption.