Min Hyuk Choi

Transparent Flexible Circuits Based on Amorphous-Indium–Gallium–Zinc–Oxide Thin-Film Transistors

Circuits implemented with high-performance amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) are realized on polyimide/polyethylene-terephthalate plastic substrates. The TFTs on plastic exhibit a saturation mobility of 19 cm2/V·s and a gate voltage swing of ~0.14 V/dec. For an input of 20 V, an 11-stage ring oscillator operates at 94.8 kHz with a propagation delay time of 0.48 μs. A shift register, consisting of ten TFTs and one capacitor, operates well with good bias stability. AC driving of pull-down TFTs gives the gate driver an improved lifetime of over ten years.

A Full-Swing a-IGZO TFT-Based Inverter With a Top-Gate-Bias-Induced Depletion Load

A high-performance inverter implemented with single-gated driving and dual-gated load amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) is demonstrated. The threshold voltage of the load TFT shifts to the negative gate voltage direction when a constant positive bias is applied on the top gate while sweeping the bottom gate. Using a positive top gate bias, the load TFT can be operated in the depletion mode to realize inverters with excellent switching characteristics, such as a wider swing range and a higher noise margin.

High-Performance Drain-Offset a-IGZO Thin-Film Transistors

We report the effect of the drain-offset length on the performance of amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). While the field-effect mobility decreases from ~ 40 to 10 cm2/V·s by increasing the drain-offset length from 0 to 5 μm, the threshold voltage (Vth) and swing (S) remain relatively independent of the offset length variation. Because of its high mobility even for large (5 μm ) offset lengths, the drain-offset a-IGZO TFT can be used to eliminate the kickback voltage in active-matrix displays.

Degradation Model of Self-Heating Effects in Silicon-on-Glass TFTs

This paper investigates the origin and reduction of self-heating effects in single-crystal silicon-on-glass (SiOG) thin-film transistors (TFTs). A hump forms in the transfer characteristics of p-channel SiOG TFTs when the temperature of the devices is increased either by direct heating or electrical biasing. The size of the hump proportionally scales with the channel width W, indicating that it is related to the bulk active-layer properties such as conduction through a backchannel. While the hump increases in the positive direction, the main transistor shifts in the negative direction with increasing self-heating stress time, supporting the exclusion of edge effects. The time dependence of the hump shift is well described by the stretched-exponential behavior, indicating that the backchannel is a result of electron trapping into the silica layer that is between the glass and silicon active layer. To mitigate this hump effect, we demonstrate in this paper that TFTs with an active layer divided into smaller parts along the W direction (in order to increase heat dissipation) show better stability to self-heating stress (i.e., no hump formation) than TFTs with full active layers. Split devices have more channel edges, compared with those with a full active layer, supporting the idea that the hump is indeed not due to edge effects.

P‐13: A Full‐Swing a‐IGZO TFT‐Based Inverter with a Top Gate‐Induced Depletion Load

A high performance amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT)-based inverter is demonstrated using the dual gate TFT structure. The results indicate that the load of the inverter behaves like a depletion-mode TFT when the top gate is under a positive bias. The proposed inverter shows much improved switching characteristics such as a wider swing range and higher noise margins, which are all achieved without the requirement of an additional process step to make the depletion load.

Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼251 and 201 cm2/V·s respectively, and threshold voltages of approximately ―0.3 and ―1.2 V for the n- and p-channet TFTs respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 x 1013, 2 x 1013, and 3 x 1013 cm―2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.

Low Voltage Driven CMOS Circuits Based on Silicon on Glass

Low voltage driven inverter, ring oscillator and shift registor circuits using n- and p- channel TFTs based on Corning® Siliconon-Glass (SiOG) substrates are studied. The field effect mobility of n- and p-channel TFTs fabricated in SiOG are 226 and 165 cm 2 /V·s, respectively. The TFTs exhibited symmetric threshold voltages of ± 1.1 V and gate voltage swings of 0.21 ~ 0.23 V/dec. The total propagation delay time of the CMOS inverter was 2.54 ns at a supply voltage of 7 V. In addition, the rise and fall times of the shift register were found to be 0.5 µs and 0.7 µs at a VDD of 7 V, respectively. This work demonstrates the the ability to realize high performance integrated CMOS circuits on SiOG substrates.