Min Ki Ryu

Photon-accelerated negative bias instability involving subgap states creation in amorphous In–Ga–Zn–O thin film transistor

We investigated the visible photon accelerated negative bias instability (NBI) in amorphous In–Ga–Zn–O (a-IGZO) thin film transistor (TFT). As reported in previous works, the rigid shift in transfer curves with insignificant changes in field-effect mobility and subthreshold swing was observed. On the other hand, there is substantial change in capacitance-voltage characteristics caused by created subgap states. The suggested nature of created states is the ionized oxygen vacancy (VO2+) by the combination of visible light and negative bias. The generated VO2+ states enhance the NBI under illumination as increased deep hole trapping centers. Furthermore, the photoexcitation of VO to stable VO2+ yields excess free carriers in conduction band. The increased carrier density also enhances the negative shift in turn-on voltage of a-IGZO TFT.

Transparent Al–Zn–Sn–O thin film transistors prepared at low temperature

We have fabricated transparent bottom gate thin film transistors (TFTs) using Al-doped zinc tin oxide (AZTO) as active layers. The AZTO active layer was deposited by rf magnetron sputtering at room temperature. The AZTO TFT showed good TFT performance without postannealing. The field effect mobility and the subthreshold swing were improved by postannealing below 180 °C. The AZTO TFT exhibited a field effect mobility (μFET) of 10.1 cm2/V s, a turn-on voltage (Von) of 0.4 V, a subthreshold swing (S/S) of 0.6 V/decade, and an on/off ratio (Ion/Ioff) of 109.

Deep-level defect characteristics in pentacene organic thin films

Organic thin-film transistors using the pentacene as an active electronic material have shown the mobility of 0.8 cm2/V s and the grains larger than 1 μm. To study the characteristics of electronic charge concentrations and the interface traps of the pentacene thin films, the capacitance properties were measured in the metal/insulator/organic semiconductor structure device by employing the capacitance–voltage and deep-level transient spectroscopy (DLTS) measurements. Based on the DLTS measurements, the concentrations and the energy levels of hole and electron traps in the obtained pentacene films were formed to be approximately 4.2×1015 cm−3 at Ev+0.24 eV, 9.6×1014 cm−3 at Ev+1.08 eV, 6.5×1015  cm−3 at Ev+0.31 eV and 2.6×1014 cm−3 at Ec−0.69 eV.

Improvement in the photon-induced bias stability of Al–Sn–Zn–In–O thin film transistors by adopting AlOx passivation layer

This study examined the impact of the passivation layer on the light-enhanced bias instability of Al–Sn–Zn–In–O (AT–ZIO) thin film transistors. The suitably passivated device exhibited only a threshold voltage (Vth) shift of 0.72 V under light-illuminated negative-thermal stress conditions, whereas the device without a passivation layer suffered from a huge negative Vth shift of >11.5 V under identical conditions. The photocreated hole trapping model could not itself explain this behavior. Instead, the light-enhanced Vth instability of the unpassivated device would result mainly from the photodesorption of adsorbed oxygen ions after exposing the AT–ZIO back-surface in an ambient atmosphere.

Impact of Sn/Zn ratio on the gate bias and temperature-induced instability of Zn-In-Sn-O thin film transistors

We investigated the effect of the Sn/Zn ratio in the amorphous Zn-In-Sn-O (ZITO) system on the gate voltage stress-induced stability of the resulting thin film transistors (TFTs). The device stability of the TFTs with a composition channel of Zn:In:Sn=0.35:0.20:0.45 (device C) was dramatically improved, while those of the devices with Zn:In:Sn=0.45:0.20:0.35 and 0.40:0.20:0.40 suffered from deep level trap creation in the channel and charge trapping, respectively. The stability enhancement of device C can be attributed to its having the lowest total trap density, which was corroborated by the superior temperature stability of the subthreshold current region in the temperature range from 298 to 398 K. Therefore, the Sn atoms are believed to act as a stabilizer of the amorphous ZITO network, which is similar to the role of Ga in the In-Ga-Zn-O system.

High performance thin film transistor with cosputtered amorphous Zn-In-Sn-O channel: Combinatorial approach

Thin film transistors with a channel of Zn–In–Sn–O were fabricated via a combinatorial rf sputtering method. It was found that the role of the In atoms is to enhance the mobility and to shift the threshold voltage (Vth) negatively. On the other hand, the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface. The optimized transistor was obtained at a compositional ratio of Zn:In:Sn=40:20:40, which exhibited an excellent subthreshold gate swing of 0.12 V/decade, Vth of −0.4 V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 24.6 cm2/V s.

Transition of dominant instability mechanism depending on negative gate bias under illumination in amorphous In-Ga-Zn-O thin film transistor

The gate bias dependence on the negative bias instability under illumination was examined. As the gate bias got more negative, dominant mechanism was changed from simple charge trapping to that accompanied by generation of subgap states. Degree of threshold voltage shift was not monotonously dependent on the magnitude of negative gate bias. It is strongly related with the corresponding instability modes for different gate bias regimes. The transition of instability mechanism depends on how much the gate bias stabilizes ionized oxygen vacancy states.

Postgrowth annealing effect on structural and optical properties of ZnO films grown on GaAs substrates by the radio frequency magnetron sputtering technique

High-resolution scanning electron microscopy and cathodoluminescence spectroscopy measurements were performed to study the effect of postgrowth annealing on properties of ZnO films grown on GaAs substrates by rf sputtering. The films annealed at 550 °C show a well-oriented columnar structure and strong exciton emission at room temperature. Outdiffusion of gallium and arsenic from substrate into a ZnO film has been found to result in a different secondary electron dopant contrast, measured by the through-the lens secondary electron detector. Extended structural defects such as subgrain boundaries in ZnO assist Ga outdiffusion from the GaAs substrate and show a reduced secondary electron (SE) emission after annealing, while As doped ZnO adjacent to the ZnO/GaAs interface demonstrates an enhanced SE emission and the enhanced luminescence associated with donor–acceptor pairs and exciton bound to acceptors.

High-Performance Al–Sn–Zn–In–O Thin-Film Transistors: Impact of Passivation Layer on Device Stability

We fabricated high-performance thin-film transistors (TFTs) with an amorphous-Al-Sn-Zn-In-O (a-AT-ZIO) channel deposited by cosputtering using a dual Al-Zn-O and In-Sn-O target. The fabricated AT-ZIO TFTs, which feature a bottom-gate and bottom-contact configuration, exhibited a high field-effect mobility of 31.9 cm2/V·s, an excellent subthreshold gate swing of 0.07 V/decade, and a high I on/off ratio of >109, even below the process temperature of 250°C. In addition, we demonstrated that the temperature and bias-induced stability of the bottom-gate TFT structure can significantly be improved by adopting a suitable passivation layer of atomic-layer-deposition-derived Al2O3 thin film.

Low-Temperature Processed Flexible In–Ga–Zn–O Thin-Film Transistors Exhibiting High Electrical Performance

In-Ga-Zn-O thin-film transistors processed at 150°C on laminated polyethylene naphthalate substrates exhibit ing high electrical performances such as a saturation mobility of 24.26 cm2/(V · s), a subthreshold slope of 140 mV/dec, a turn-on voltage Von of -0.41 V, and an on-off ratio of 1.8 × 109 were fabricated. Cool-off-type adhesive was adopted to easily detach the plastic substrate from the carrier holder. Devices also showed highly uniform characteristics with a variation of 0.09 V in turn-on voltage. Stability characteristics under the positive gate bias stress can be enhanced by increasing the annealing time at 150°C.